公开(公告)号：US20170146578A1

公开(公告)日：2017-05-25

申请号：US15139801

申请日：2016-04-27

Applicant: STMICROELECTRONICS SA

Inventor： Marc HOUDEBINE ,  Sebastien Dedieu

IPC: G01R23/10

CPC classification number: G01R23/10 ,  G01R23/02 ,  H03D13/001

Abstract: A method includes a) counting whole periods of a signal during a first period of a reference signal, b) repeating step a) for each period of the reference signal until a first duration is equal to a first quantity of periods of the reference signal, and c) determining a first average of the whole periods. The method also includes repeating at least one of steps a) to c) and at each repetition shifting a start of the counting of step a) by at least one period of the reference signal, and in steps b) and c) accounting for whole periods of the signal already counted during the at least one preceding group of steps a) and b). The method includes determining a second average of the first averages, and determining the frequency of the signal from the second average and the frequency of the reference signal.

公开(公告)号：US20090108879A1

公开(公告)日：2009-04-30

申请号：US11928080

申请日：2007-10-30

Applicant: Ram Kelkar ,  Grant P. Kesselring

Inventor： Ram Kelkar ,  Grant P. Kesselring

IPC: G01R23/15

CPC classification number: G01R23/005 ,  H03D13/001

Abstract: A frequency coincidence detection circuit for detecting frequency edges for each of a plurality of periodic digital signals. The circuit generates count indicators for each of the periodic digital signals and compares each of the count indicators to a programmable sensitivity input to determine a coincidence window for the corresponding one of each of the periodic digital signals. The circuit determines a signal coincidence of the coincidence windows. In another embodiment, a frequency coincidence detection method is provided. The method detects frequency edges for each of a plurality of periodic digital signals, generates count indicators for each of the periodic digital signals and compares each of the count indicators to a programmable sensitivity input to determine a coincidence window for the corresponding one of each of the periodic digital signals. The method determines a signal coincidence of the coincidence windows.

Abstract translation: 一种用于检测多个周期数字信号中的每一个的频率边缘的频率一致检测电路。 电路产生每个周期性数字信号的计数指示器，并将每个计数指示器与可编程灵敏度输入进行比较，以确定每个周期性数字信号中的相应一个的一致窗口。 电路确定符合窗口的信号重合。 在另一个实施例中，提供了一种频率一致检测方法。 该方法检测多个周期性数字信号中的每一个的频率边缘，为每个周期性数字信号产生计数指示符，并将每个计数指示符与可编程灵敏度输入进行比较，以确定每个周期数字信号中的每一个的相应窗口 周期性数字信号。 该方法确定符合窗口的信号重合。

公开(公告)号：US20040100308A1

公开(公告)日：2004-05-27

申请号：US10375587

申请日：2003-02-27

Applicant: Sun Microsystems, Inc.

Inventor： Massimo Sutera ,  David A. Bunsey JR. ,  Daniel Y. Cheung ,  Lan Lee ,  Kevin B. Normoyle ,  Sung-Hun Oh ,  Shi-Chin Ou-Yang ,  Fabrizio Romano ,  Ivana Cappellano

IPC: H03D013/00

CPC classification number: H03D13/001

Abstract: In an embodiment, present application describes a system and method to detect the alignment of multiple clocks in multi-clock domains system. In some variations, multiple clocks are derived from one or more reference clocks using various PLLs. The derived clocks maintain frequency relationship with the reference clock. In some variations, a relationship between the frequencies of various clocks is used to generate the alignment signals in the domain of one of the clocks.

Abstract translation: 在一个实施例中，本申请描述了一种用于检测多时钟域系统中多个时钟的对准的系统和方法。 在一些变型中，使用各种PLL从一个或多个参考时钟导出多个时钟。 导出的时钟与参考时钟保持频率关系。 在一些变型中，使用各种时钟的频率之间的关系来产生其中一个时钟的域中的对准信号。

公开(公告)号：US06735265B1

公开(公告)日：2004-05-11

申请号：US09614208

申请日：2000-07-11

Applicant: Akira Yasuda

Inventor： Akira Yasuda

IPC: H03D324

CPC classification number: H03D13/001

Abstract: A comparator compares a first binary input signal and a second binary input signal each binalized. A generator generates a reset signal at each rising edge or each falling edge of the first input signal. A counter counts the second input signal at each timing determined by the reset signal. The counted value represents a ratio of each frequency of the first input signal and the second input signal. A subtractor calculates a difference between the counted value and a set value representing a predetermined ratio of each frequency of the first input signal and the second input signal. An integrator integrates the difference. The integrated value represents a phase difference of the frequencies of the first input signal and the second input signal.

Abstract translation: 比较器比较第一二进制输入信号和每个二进制的第二二进制输入信号。 发生器在第一输入信号的每个上升沿或每个下降沿产生复位信号。 计数器在由复位信号确定的每个定时对第二输入信号进行计数。 计数值表示第一输入信号和第二输入信号的每个频率的比率。 减法器计算计数值和​​表示第一输入信号和第二输入信号的每个频率的预定比率的设定值之间的差。 集成商整合差异。 积分值表示第一输入信号和第二输入信号的频率的相位差。

公开(公告)号：US5484987A

公开(公告)日：1996-01-16

申请号：US286129

申请日：1994-08-04

Applicant: Toshiharu Kojima

Inventor： Toshiharu Kojima

IPC: H04L27/38 ,  H03D7/00 ,  H03D7/16 ,  H03D13/00 ,  H04L27/22 ,  H04L27/227 ,  H04L27/233

CPC classification number: H03D7/00 ,  H03D13/001 ,  H03D13/003 ,  H04L27/2332 ,  H04L27/2337 ,  H03D2200/007 ,  H03D7/161 ,  H03D7/165

Abstract: Within the differential detection demodulator, the received signal is first quantized by a limiter amplifier and then subjected to frequency conversion by a frequency converter including: an exclusive OR element; a running average generator consisting of a shift register and an adder; and a comparator. In response to the output of the frequency converter, the phase comparator outputs a relative phase signal representing the phase shift of the received signal after frequency conversion relative to the phase signal representing the phase shift of the received signal after frequency conversion relative to the phase reference signal. The phase comparator includes: an exclusive OR element; an absolute phase shift measurement means consisting of an adder and D flip-flop arrays and; and a D flip-flop serving as a phase shift polarity decision means. Alternatively, the phase detection circuit for generating the relative phase signal may include: a half-period detection means consisting of a delay element and an exclusive OR element; a phase reference signal generation means consisting of a modulo 2N counter; and a phase shift measurement means consisting of a phase inversion corrector and a D flip-flop array. The delay element delays the relative phase signal by one symbol period and the subtractor outputs the phase difference signal representing the phase transition over each symbol period of the received signal. The decision circuit obtains the demodulated data from the phase difference signal.

Abstract translation: 在差分检测解调器中，接收信号首先由限幅放大器量化，然后由包括：异或元素的变频器进行频率转换; 由移位寄存器和加法器组成的运行平均发生器; 和比较器。 响应于变频器的输出，相位比较器输出表示频率转换后的接收信号的相移相对于表示频率转换后的接收信号相对于相位参考的相移的相位信号的相对相位信号 信号。 相位比较器包括：异或元件; 由加法器和D触发器阵列组成的绝对相移测量装置; 以及用作相移极性判定装置的D触发器。 或者，用于产生相对相位信号的相位检测电路可以包括：由延迟元件和异或元件组成的半周期检测装置; 由2N模计数器组成的相位参考信号产生装置; 以及由相位反相校正器和D触发器阵列组成的相移测量装置。 延迟元件将相对相位信号延迟一个符号周期，并且减法器输出表示接收信号的每个符号周期上的相位转换的相位差信号。 决定电路从相位差信号中获得解调数据。

公开(公告)号：US5313170A

公开(公告)日：1994-05-17

申请号：US997768

申请日：1992-12-24

Applicant: Toshiharu Kojima

Inventor： Toshiharu Kojima

IPC: H03D7/00 ,  H03D7/16 ,  H03D13/00 ,  H04L27/233 ,  H04L27/22

CPC classification number: H04L27/2332 ,  H03D13/001 ,  H03D13/003 ,  H03D7/00 ,  H04L27/2337 ,  H03D2200/007 ,  H03D7/161 ,  H03D7/165

Abstract: Within the differential detection demodulator, the received signal is first quantized by a limiter amplifier 10 and then subjected to frequency conversion by a frequency converter 50 including: an exclusive OR element 51; a running average generator 52 consisting of a shift register 53 and an adder 54; and a comparator 55. In response to the output of the frequency converter 50, the phase comparator 60 outputs a relative phase signal representing the phase shift of the received signal after frequency conversion relative to the phase reference signal. The phase comparator 60 includes: an exclusive OR element 61; an absolute phase shift measurement means 62 consisting of an adder 63 and D flip-flop arrays 64 and 65; and a D flip-flop 66 serving as a phase shift polarity decision means. Alternatively, the phase detection circuit 400 for generating the relative phase signal may include: a half-period detection means 901 consisting of a delay element 401 and an exclusive OR element 402; a phase reference signal generation means 902 consisting of a modulo 2N counter 403; and a phase shift measurement means 903 consisting of a phase inversion corrector 500 and a D flip-flop array 404. The delay element 40 delays the relative phase signal by one symbol period and the subtractor 41 outputs the phase difference signal representing the phase transition over each symbol period of the received signal. The decision circuit 42 obtains the demodulated data from the phase difference signal.

Abstract translation: 在差分检测解调器中，接收信号首先由限幅放大器10量化，然后由包括：异或元件51的变频器50进行频率转换; 由移位寄存器53和加法器54组成的运行平均发生器52; 和比较器55.响应于频率转换器50的输出，相位比较器60相对于相位参考信号输出表示频率转换之后的接收信号的相移的相对相位信号。 相位比较器60包括：异或元件61; 由加法器63和D触发器阵列64和65组成的绝对相移测量装置62; 以及用作相移极性判定装置的D触发器66。 或者，用于产生相对相位信号的相位检测电路400可以包括：由延迟元件401和异或元件402组成的半周期检测装置901; 由模2N计数器403组成的相位参考信号产生装置902; 以及由相位反相校正器500和D触发器阵列404组成的相移测量装置903.延迟元件40将相对相位信号延迟一个符号周期，并且减法器41输出表示相位转变的相位差信号 接收信号的每个符号周期。 判定电路42从相位差信号中取得解调数据。

公开(公告)号：US5289505A

公开(公告)日：1994-02-22

申请号：US806511

申请日：1991-12-13

Applicant: Christopher P. LaRosa ,  Michael J. Carney

Inventor： Christopher P. LaRosa ,  Michael J. Carney

IPC: H04L27/233 ,  A61F13/15 ,  H03D7/00 ,  H03D13/00 ,  H04L27/22

CPC classification number: H03D7/00 ,  H03D13/001 ,  H03D2200/005 ,  H03D2200/006 ,  H03D2200/007

Abstract: The present patent application discusses a frequency translation apparatus for altering the effective frequency of the phase information of an input signal (115). The input signal (115) has a first phase (.theta.(t)) and a first frequency (f.sub.i). The phase of the input signal is extracted and digitized at a second frequency (f.sub.o), forming a second N-bit digital phase signal (.theta.'(t))(311). The frequency translation apparatus generates a third digital phase signal (319) which approximates the difference between .theta.(t) and .theta.'(t). Then, the frequency translation apparatus combines the second digital phase signal and the third digital phase signal, forming a fourth digital phase signal (307) substantially approximating the first phase signal.

Abstract translation: 本专利申请讨论了用于改变输入信号（115）的相位信息的有效频率的频率转换装置。 输入信号（115）具有第一相位（（θ）（t））和第一频率（fi）。 输入信号的相位被提取并以第二频率（fo）数字化，形成第二N位数字相位信号（（θ）'（t））（311）。 频率转换装置产生近似（θ）（t）和（θ）'（t）之间的差的第三数字相位信号（319）。 然后，频率转换装置组合第二数字相位信号和第三数字相位信号，形成基本上接近第一相位信号的第四数字相位信号（307）。

公开(公告)号：US5241567A

公开(公告)日：1993-08-31

申请号：US724184

申请日：1991-07-01

Applicant: Yukihiro Shimakata

Inventor： Yukihiro Shimakata

IPC: H04L27/227 ,  H03D13/00 ,  H04L27/00 ,  H04L27/233

CPC classification number: H04L27/2332 ,  H03D13/001 ,  H04L27/2337 ,  H04L2027/003 ,  H04L2027/0053

Abstract: In a differential-detection demodulator circuit, a PSK modulated signal is compared with a locally oscillated signal to obtain a phase difference between the two signals, whereupon the phase difference is demodulated. A phase detector circuit of the digital type outputs the phase difference signal. The digital phase comparator circuit compares plural reference signals, which give predetermined delays to the locally oscillated signals having carrier frequencies, with the inputted modulated signals. Preferably, a pulse signal having a phase difference between the inputted modulated signal and the locally oscillated signal is produced, and the pulse width of this pulse signal is measured by a counter. By digitalizing the entire phase comparator, it is possible to realize demodulation with low electrical power consumption and simple circuit construction.

公开(公告)号：US20240364353A1

公开(公告)日：2024-10-31

申请号：US18768179

申请日：2024-07-10

Applicant: Allegro MicroSystems, LLC

Inventor： Florencia Ferrer ,  Lucas Intile ,  Juan Manuel Cesaretti ,  Nicolás Rigoni

IPC: H03L7/099 ,  H03D13/00 ,  H03K3/12

CPC classification number: H03L7/0991 ,  H03D13/001 ,  H03K3/12

Abstract: Clock monitors for circuits having a plurality of oscillators. The clock monitors produce an error indication when one oscillator is determined to be outside of a desired operating range or beyond a defined threshold with respect to a second oscillator. The clock monitors include a synchronizer configured to receive a clock signal from a first oscillator of the plurality of oscillators and synchronize the received clock signal with a second oscillator and to produce a synchronized clock signal. The clock monitors can include a counter configured to produce a count value based on synchronized clock signal. The clock monitors include comparison circuitry configured to receive the count value and produce an error indication when the count value is outside a predetermined range. The clock monitors may be used to ensure correct clock operation for different transition scenarios, e.g., turning on or off a certain clock or power domain.

公开(公告)号：US12063046B2

公开(公告)日：2024-08-13

申请号：US18063809

申请日：2022-12-09

Applicant: Allegro MicroSystems, LLC

Inventor： Florencia Ferrer ,  Lucas Intile ,  Juan Manuel Cesaretti ,  Nicolás Rigoni

IPC: H03L7/00 ,  H03D13/00 ,  H03K3/12 ,  H03L7/099

CPC classification number: H03L7/0991 ,  H03D13/001 ,  H03K3/12

Abstract: Clock monitors for circuits having a plurality of oscillators. The clock monitors produce an error indication when one oscillator is determined to be outside of a desired operating range or beyond a defined threshold with respect to a second oscillator. The clock monitors include a synchronizer configured to receive a clock signal from a first oscillator of the plurality of oscillators and synchronize the received clock signal with a second oscillator and to produce a synchronized clock signal. The clock monitors can include a counter configured to produce a count value based on synchronized clock signal. The clock monitors include comparison circuitry configured to receive the count value and produce an error indication when the count value is outside a predetermined range. The clock monitors may be used to ensure correct clock operation for different transition scenarios, e.g., turning on or off a certain clock or power domain.