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公开(公告)号：US20220179013A1
公开(公告)日：2022-06-09
申请号：US17112107
申请日：2020-12-04
Applicant: Allegro MicroSystems, LLC
Inventor： Sergio Nicolás Deligiannis , Nicolás Rigoni
Abstract: According to some embodiments, a method implemented in electronic circuitry includes: receiving a first signal having a sinusoidal waveform; receiving a second signal having a sinusoidal waveform; generating a composite signal responsive to the first and second signals; determining an orthogonality adjustment coefficient based on a duty cycle of the composite signal; and applying the orthogonality adjustment coefficient to generate an adjusted second signal that is substantially orthogonal to the first signal.
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公开(公告)号：US20240110777A1
公开(公告)日：2024-04-04
申请号：US17936469
申请日：2022-09-29
Applicant: Allegro MicroSystems, LLC
Inventor： Emanuele Andrea Casu , Nicolás Rigoni , Ross Eisenbeis
Abstract: Methods and apparatus receiving data at a first time from at least one sensor, determining a parameter from the received data for the first time, estimating the parameter for a future time based on the data for first time, and outputting the estimated parameter for the future time to a receiving device. In some embodiments, an IC package can process the received data to generate the estimated parameter for the future time. The IC package may transmit the estimated parameter using a particular protocol. In some embodiments, the receiving device can treat the estimated parameter as real-time data.
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公开(公告)号：US12107710B2
公开(公告)日：2024-10-01
申请号：US17658872
申请日：2022-04-12
Applicant: Allegro MicroSystems, LLC
Inventor： Emanuele Andrea Casu , Cédric Gillet , Nicolás Rigoni , Florencia Ferrer , Andreas P. Friedrich , Emil Pavlov
CPC classification number: H04L25/4902 , G07C5/0808 , H04L1/0042 , H04L7/048
Abstract: A sensor integrated circuit (IC) includes a sensing element configured to sense a parameter associated with a target, a processor coupled to the sensing element and configured to generate a sensed signal indicative of the parameter associated with the target, and an output module coupled to receive the sensed signal. The output module is configured to transmit absolute data on a message line at a first rate and transmit incremental data on one or more index lines at a second rate, wherein the second rate is faster than the first rate, wherein the incremental data comprises data associated with changes in the absolute data and wherein an edge or a pulse is used to indicate an incremental change has occurred in the absolute data.
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公开(公告)号：US12104900B2
公开(公告)日：2024-10-01
申请号：US17936469
申请日：2022-09-29
Applicant: Allegro MicroSystems, LLC
Inventor： Emanuele Andrea Casu , Nicolás Rigoni , Ross Eisenbeis
Abstract: Methods and apparatus receiving data at a first time from at least one sensor, determining a parameter from the received data for the first time, estimating the parameter for a future time based on the data for first time, and outputting the estimated parameter for the future time to a receiving device. In some embodiments, an IC package can process the received data to generate the estimated parameter for the future time. The IC package may transmit the estimated parameter using a particular protocol. In some embodiments, the receiving device can treat the estimated parameter as real-time data.
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公开(公告)号：US11555716B1
公开(公告)日：2023-01-17
申请号：US17505707
申请日：2021-10-20
Applicant: Allegro MicroSystems, LLC
Inventor： Nicolás Rigoni , Cristian Trinidad , Emanuele Andrea Casu
Abstract: A magnetic field sensor configured to sense a parameter associated with a rotatable target that affects a magnetic field includes at least one magnetic field sensing element that is arranged to generate a signal that is indicative of the magnetic field, a magnitude calculator responsive to the signal and configured to generate a magnitude signal indicative of a magnitude of the magnetic field, and a harmonic compensator responsive to the magnitude signal and configured to generate an estimate of a harmonic error of the signal and apply the estimate of the harmonic error of the signal to the signal to generate a corrected signal.
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Patent Agency Ranking
公开(公告)号：US20240195424A1
公开(公告)日：2024-06-13
申请号：US18063809
申请日：2022-12-09
Applicant: Allegro MicroSystems, LLC
Inventor： Florencia Ferrer , Lucas Intile , Juan Manuel Cesaretti , Nicolás Rigoni
CPC classification number: H03L7/0991 , H03D13/001 , H03K3/12
Abstract: Clock monitors for circuits having a plurality of oscillators. The clock monitors produce an error indication when one oscillator is determined to be outside of a desired operating range or beyond a defined threshold with respect to a second oscillator. The clock monitors include a synchronizer configured to receive a clock signal from a first oscillator of the plurality of oscillators and synchronize the received clock signal with a second oscillator and to produce a synchronized clock signal. The clock monitors can include a counter configured to produce a count value based on synchronized clock signal. The clock monitors include comparison circuitry configured to receive the count value and produce an error indication when the count value is outside a predetermined range. The clock monitors may be used to ensure correct clock operation for different transition scenarios, e.g., turning on or off a certain clock or power domain.
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公开(公告)号：US20220390257A1
公开(公告)日：2022-12-08
申请号：US17331981
申请日：2021-05-27
Applicant: Allegro MicroSystems, LLC
Inventor： Sergio Nicolás Deligiannis , Nicolás Rigoni
Abstract: A sensor, comprising: a processing circuitry configured to: receive a first signal that is generated by a first magnetic field sensing element, the first signal being generated in response to a magnetic field that is indicative of rotation of a target; identify N local maxima of the first signal, where N is a positive integer, and N>1; identify N local minima of the first signal; generate a first offset adjustment signal and a first gain adjustment signal based on: (i) a first sum of the local maxima of the first signal and (ii) a second sum of the local minima of the first signal; and adjust the first signal based on the first offset adjustment signal and the first gain adjustment signal.
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公开(公告)号：US11480630B2
公开(公告)日：2022-10-25
申请号：US17112107
申请日：2020-12-04
Applicant: Allegro MicroSystems, LLC
Inventor： Sergio Nicolás Deligiannis , Nicolás Rigoni
Abstract: According to some embodiments, a method implemented in electronic circuitry includes: receiving a first signal having a sinusoidal waveform; receiving a second signal having a sinusoidal waveform; generating a composite signal responsive to the first and second signals; determining an orthogonality adjustment coefficient based on a duty cycle of the composite signal; and applying the orthogonality adjustment coefficient to generate an adjusted second signal that is substantially orthogonal to the first signal.
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公开(公告)号：US20240364353A1
公开(公告)日：2024-10-31
申请号：US18768179
申请日：2024-07-10
Applicant: Allegro MicroSystems, LLC
Inventor： Florencia Ferrer , Lucas Intile , Juan Manuel Cesaretti , Nicolás Rigoni
CPC classification number: H03L7/0991 , H03D13/001 , H03K3/12
Abstract: Clock monitors for circuits having a plurality of oscillators. The clock monitors produce an error indication when one oscillator is determined to be outside of a desired operating range or beyond a defined threshold with respect to a second oscillator. The clock monitors include a synchronizer configured to receive a clock signal from a first oscillator of the plurality of oscillators and synchronize the received clock signal with a second oscillator and to produce a synchronized clock signal. The clock monitors can include a counter configured to produce a count value based on synchronized clock signal. The clock monitors include comparison circuitry configured to receive the count value and produce an error indication when the count value is outside a predetermined range. The clock monitors may be used to ensure correct clock operation for different transition scenarios, e.g., turning on or off a certain clock or power domain.
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公开(公告)号：US12063046B2
公开(公告)日：2024-08-13
申请号：US18063809
申请日：2022-12-09
Applicant: Allegro MicroSystems, LLC
Inventor： Florencia Ferrer , Lucas Intile , Juan Manuel Cesaretti , Nicolás Rigoni
CPC classification number: H03L7/0991 , H03D13/001 , H03K3/12
Abstract: Clock monitors for circuits having a plurality of oscillators. The clock monitors produce an error indication when one oscillator is determined to be outside of a desired operating range or beyond a defined threshold with respect to a second oscillator. The clock monitors include a synchronizer configured to receive a clock signal from a first oscillator of the plurality of oscillators and synchronize the received clock signal with a second oscillator and to produce a synchronized clock signal. The clock monitors can include a counter configured to produce a count value based on synchronized clock signal. The clock monitors include comparison circuitry configured to receive the count value and produce an error indication when the count value is outside a predetermined range. The clock monitors may be used to ensure correct clock operation for different transition scenarios, e.g., turning on or off a certain clock or power domain.
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