Method and circuitry for phase align detection in multi-clock domain
    1.
    发明申请
    Method and circuitry for phase align detection in multi-clock domain 有权
    用于多时钟域中相位校准检测的方法和电路

    公开(公告)号:US20040100308A1

    公开(公告)日:2004-05-27

    申请号:US10375587

    申请日:2003-02-27

    CPC classification number: H03D13/001

    Abstract: In an embodiment, present application describes a system and method to detect the alignment of multiple clocks in multi-clock domains system. In some variations, multiple clocks are derived from one or more reference clocks using various PLLs. The derived clocks maintain frequency relationship with the reference clock. In some variations, a relationship between the frequencies of various clocks is used to generate the alignment signals in the domain of one of the clocks.

    Abstract translation: 在一个实施例中,本申请描述了一种用于检测多时钟域系统中多个时钟的对准的系统和方法。 在一些变型中,使用各种PLL从一个或多个参考时钟导出多个时钟。 导出的时钟与参考时钟保持频率关系。 在一些变型中,使用各种时钟的频率之间的关系来产生其中一个时钟的域中的对准信号。

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