公开(公告)号：US09563575B2

公开(公告)日：2017-02-07

申请号：US14929645

申请日：2015-11-02

Applicant: Apple Inc.

Inventor： Brian P. Lilly ,  Gerard R. Williams, III ,  Mahnaz Sadoughi-Yarandi ,  Perumal R. Subramonium ,  Hari S. Kannan ,  Prashant Jain

IPC: G06F12/08 ,  G06F12/12

CPC classification number: G06F12/123 ,  G06F12/0862 ,  G06F12/0897 ,  G06F12/127 ,  G06F2212/1021

Abstract: A mechanism for evicting a cache line from a cache memory includes first selecting for eviction a least recently used cache line of a group of invalid cache lines. If all cache lines are valid, selecting for eviction a least recently used cache line of a group of cache lines in which no cache line of the group of cache lines is also stored within a higher level cache memory such as the L1 cache, for example. Lastly, if all cache lines are valid and there are no non-inclusive cache lines, selecting for eviction the least recently used cache line stored in the cache memory.

Abstract translation: 用于从高速缓冲存储器中逐出高速缓存行的机制包括首先选择驱逐一组无效高速缓存行的最近最少使用的高速缓存行。 如果所有高速缓存行都有效，则选择驱逐，一组高速缓存行的最近最少使用的高速缓存行，其中该高速缓存行组中的高速缓存行也不存储在诸如L1高速缓存的更高级高速缓冲存储器中 。 最后，如果所有高速缓存行都是有效的，并且没有非包含的高速缓存行，则选择驱逐存储在高速缓冲存储器中的最近最少使用的高速缓存行。

公开(公告)号：US09047198B2

公开(公告)日：2015-06-02

申请号：US13689696

申请日：2012-11-29

Applicant: Apple Inc.

Inventor： Hari S. Kannan ,  Pradeep Kanapathipillai ,  Brian P. Lilly ,  Perumal R. Subramoniam ,  Mahnaz Sadoughi-Yarandi

IPC: G06F12/00 ,  G06F12/08 ,  G06F13/00 ,  G06F13/28 ,  G06F9/26 ,  G06F9/34 ,  G06F12/10

CPC classification number: G06F12/0862 ,  G06F12/0811 ,  G06F12/1027 ,  G06F2212/6026 ,  G06F2212/654 ,  G06F2212/655

Abstract: Processors and methods for preventing lower level prefetch units from stalling at page boundaries. An upper level prefetch unit closest to the processor core issues a preemptive request for a translation of the next page in a given prefetch stream. The upper level prefetch unit sends the translation to the lower level prefetch units prior to the lower level prefetch units reaching the end of the current page for the given prefetch stream. When the lower level prefetch units reach the boundary of the current page, instead of stopping, these prefetch units can continue to prefetch by jumping to the next physical page number provided in the translation.

Abstract translation: 用于防止较低级别的预取单元在页面边界停止的处理器和方法。 最靠近处理器核心的高级预取单元在给定的预取流中发出对下一页的翻译的抢占请求。 在较低级预取单元到达给定预取流的当前页面的末尾之前，高级预取单元将转换发送到较低级预取单元。 当低级预取单元到达当前页面的边界而不是停止时，这些预取单元可以通过跳转到翻译中提供的下一个物理页码继续预取。

公开(公告)号：US09529730B2

公开(公告)日：2016-12-27

申请号：US14263386

申请日：2014-04-28

Applicant: Apple Inc.

Inventor： Mahnaz Sadoughi-Yarandi ,  Perumal R. Subramonium ,  Brian P. Lilly ,  Hari S. Kannan

IPC: G06F12/12

CPC classification number: G06F12/122 ,  G06F2212/1021 ,  G06F2212/1024 ,  G06F2212/1041

Abstract: A method and apparatus for evicting cache lines from a cache memory includes receiving a request from one of a plurality of processors. The cache memory is configured to store a plurality of cache lines, and a given cache line includes an identifier indicating a processor that performed a most recent access of the given cache line. The method further includes selecting a cache line for eviction from a group of least recently used cache lines, where each cache line of the group of least recently used cache lines occupy a priority position less that a predetermined value, and then evicting the selected cache line.

Abstract translation: 用于从高速缓冲存储器中取出高速缓存行的方法和装置包括从多个处理器之一接收请求。 高速缓存存储器被配置为存储多条高速缓存行，并且给定的高速缓存行包括指示执行给定高速缓存行的最近访问的处理器的标识符。 该方法还包括从一组最近最少使用的高速缓存行中选择用于逐出的高速缓存行，其中最近最少使用的高速缓存行的组中的每个高速缓存行占据优先级位置小于预定值，然后逐出所选择的高速缓存行 。

公开(公告)号：US09513693B2

公开(公告)日：2016-12-06

申请号：US14224773

申请日：2014-03-25

Applicant: Apple Inc.

Inventor： Prashant Jain ,  Brian P. Lilly ,  Mahnaz Sadoughi-Yarandi ,  Helen Huang

IPC: G06F1/32 ,  G11C7/12 ,  G06F12/08

CPC classification number: G06F1/3275 ,  G06F1/3225 ,  G06F1/3296 ,  G06F12/0802 ,  G06F12/0846 ,  G06F12/0864 ,  G06F2212/1028 ,  G06F2212/502 ,  G06F2212/601 ,  G11C5/14 ,  G11C7/04 ,  G11C7/12 ,  G11C2207/2227 ,  Y02D10/13 ,  Y02D10/14 ,  Y02D10/172 ,  Y02D50/20

Abstract: Systems and methods for reducing leakage power in a L2 cache within a SoC. The L2 cache is partitioned into multiple banks, and each bank has its own separate power supply. An idle counter is maintained for each bank to count a number of cycles during which the bank has been inactive. The temperature and leaky factor of the SoC are used to select an operating point of the SoC. Based on the operating point, an idle counter threshold is set, with a high temperature and high leaky factor corresponding to a relatively low idle counter threshold, and with a low temperature and low leaky factor corresponding to a relatively high idle counter threshold. When a given idle counter exceeds the idle counter threshold, the voltage supplied to the corresponding bank is reduced to a voltage sufficient for retention of data but not for access.

Abstract translation: 降低SoC内二级缓存中漏电功率的系统和方法。 L2缓存分为多个银行，每个银行都有自己独立的电源。 为每个银行维护一个空闲计数器来计算银行已经不活动的周期数。 SoC的温度和泄漏因子用于选择SoC的工作点。 基于操作点，设置空闲计数器阈值，具有对应于相对低的空闲计数器阈值的高温度和高泄漏因子，以及对应于相对高的空闲计数器阈值的低温度和低泄漏因子。 当给定的空闲计数器超过空闲计数器阈值时，提供给相应存储体的电压降低到足以保留数据但不能访问的电压。

公开(公告)号：US20150309939A1

公开(公告)日：2015-10-29

申请号：US14263369

申请日：2014-04-28

Applicant: Apple Inc.

Inventor： Mahnaz Sadoughi-Yarandi ,  Perumal R. Subramonium ,  Brian P. Lilly ,  Hari S. Kannan

IPC: G06F12/08

CPC classification number: G06F12/0895 ,  G06F2212/1028 ,  Y02D10/13

Abstract: A method and apparatus for selectively powering down a portion of a cache memory includes determining a power down condition dependent upon a number of accesses to the cache memory. In response to the detection of the power down condition, selecting a group of cache ways included in the cache memory dependent upon a number of cache lines in each cache way that are also included in another cache memory. The method further includes locking and flushing the selected group of cache ways, and then activating a low power mode for the selected group of cache ways.

Abstract translation: 用于选择性地降低高速缓存存储器的一部分的方法和装置包括根据对高速缓冲存储器的访问次数确定掉电条件。 响应于断电状态的检测，根据还包括在另一个高速缓冲存储器中的每种高速缓存方式中的高速缓存行数量，选择包括在高速缓冲存储器中的一组高速缓存路。 该方法还包括锁定和刷新所选择的一组高速缓存路径，然后激活所选择的高速缓存路径组的低功率模式。

公开(公告)号：US20160055099A1

公开(公告)日：2016-02-25

申请号：US14929645

申请日：2015-11-02

Applicant: Apple Inc.

Inventor： Brian P. Lilly ,  Gerard R. Williams, III ,  Mahnaz Sadoughi-Yarandi ,  Perumal R. Subramonium ,  Hari S. Kannan ,  Prashant Jain

IPC: G06F12/12

CPC classification number: G06F12/123 ,  G06F12/0862 ,  G06F12/0897 ,  G06F12/127 ,  G06F2212/1021

Abstract: A mechanism for evicting a cache line from a cache memory includes first selecting for eviction a least recently used cache line of a group of invalid cache lines. If all cache lines are valid, selecting for eviction a least recently used cache line of a group of cache lines in which no cache line of the group of cache lines is also stored within a higher level cache memory such as the L1 cache, for example. Lastly, if all cache lines are valid and there are no non-inclusive cache lines, selecting for eviction the least recently used cache line stored in the cache memory.

公开(公告)号：US20150309944A1

公开(公告)日：2015-10-29

申请号：US14263386

申请日：2014-04-28

Applicant: Apple Inc.

Inventor： Mahnaz Sadoughi-Yarandi ,  Perumal R. Subramonium ,  Brian P. Lilly ,  Hari S. Kannan

IPC: G06F12/12

CPC classification number: G06F12/122 ,  G06F2212/1021 ,  G06F2212/1024 ,  G06F2212/1041

Abstract: A method and apparatus for evicting cache lines from a cache memory includes receiving a request from one of a plurality of processors. The cache memory is configured to store a plurality of cache lines, and a given cache line includes an identifier indicating a processor that performed a most recent access of the given cache line. The method further includes selecting a cache line for eviction from a group of least recently used cache lines, where each cache line of the group of least recently used cache lines occupy a priority position less that a predetermined value, and then evicting the selected cache line.

Abstract translation: 用于从高速缓冲存储器中取出高速缓存行的方法和装置包括从多个处理器之一接收请求。 高速缓存存储器被配置为存储多条高速缓存行，并且给定的高速缓存行包括指示执行给定高速缓存行的最近访问的处理器的标识符。 该方法还包括从一组最近最少使用的高速缓存行中选择用于逐出的高速缓存行，其中最近最少使用的高速缓存行的组中的每个高速缓存行占据优先级位置小于预定值，然后逐出所选择的高速缓存行 。

公开(公告)号：US20150026404A1

公开(公告)日：2015-01-22

申请号：US13946327

申请日：2013-07-19

Applicant: Apple Inc.

Inventor： Brian P. Lilly ,  Gerard R. Williams, III ,  Mahnaz Sadoughi-Yarandi ,  Perumal R. Subramonium ,  Hari S. Kannan ,  Prashant Jain

IPC: G06F12/08

CPC classification number: G06F12/123 ,  G06F12/0862 ,  G06F12/0897 ,  G06F12/127 ,  G06F2212/1021

Abstract: A mechanism for evicting a cache line from a cache memory includes first selecting for eviction a least recently used cache line of a group of invalid cache lines. If all cache lines are valid, selecting for eviction a least recently used cache line of a group of cache lines in which no cache line of the group of cache lines is also stored within a higher level cache memory such as the L1 cache, for example. Lastly, if all cache lines are valid and there are no non-inclusive cache lines, selecting for eviction the least recently used cache line stored in the cache memory.

Abstract translation: 用于从高速缓冲存储器中逐出高速缓存行的机制包括首先选择驱逐一组无效高速缓存行的最近最少使用的高速缓存行。 如果所有高速缓存行都有效，则选择驱逐，一组高速缓存行的最近最少使用的高速缓存行，其中该高速缓存行组中的高速缓存行也不存储在诸如L1高速缓存的更高级高速缓冲存储器中 。 最后，如果所有高速缓存行都是有效的，并且没有非包含的高速缓存行，则选择驱逐存储在高速缓冲存储器中的最近最少使用的高速缓存行。

公开(公告)号：US09176879B2

公开(公告)日：2015-11-03

申请号：US13946327

申请日：2013-07-19

Applicant: Apple Inc.

Inventor： Brian P. Lilly ,  Gerard R. Williams, III ,  Mahnaz Sadoughi-Yarandi ,  Perumal R. Subramonium ,  Hari S. Kannan ,  Prashant Jain

IPC: G06F12/08 ,  G06F12/12

CPC classification number: G06F12/123 ,  G06F12/0862 ,  G06F12/0897 ,  G06F12/127 ,  G06F2212/1021

Abstract: A mechanism for evicting a cache line from a cache memory includes first selecting for eviction a least recently used cache line of a group of invalid cache lines. If all cache lines are valid, selecting for eviction a least recently used cache line of a group of cache lines in which no cache line of the group of cache lines is also stored within a higher level cache memory such as the L1 cache, for example. Lastly, if all cache lines are valid and there are no non-inclusive cache lines, selecting for eviction the least recently used cache line stored in the cache memory.

Abstract translation: 用于从高速缓冲存储器中逐出高速缓存行的机制包括首先选择驱逐一组无效高速缓存行的最近最少使用的高速缓存行。 如果所有高速缓存行都有效，则选择驱逐，一组高速缓存行的最近最少使用的高速缓存行，其中该高速缓存行组中的高速缓存行也不存储在诸如L1高速缓存的更高级高速缓冲存储器中 。 最后，如果所有高速缓存行都是有效的，并且没有非包含的高速缓存行，则选择驱逐存储在高速缓冲存储器中的最近最少使用的高速缓存行。

公开(公告)号：US20150277541A1

公开(公告)日：2015-10-01

申请号：US14224773

申请日：2014-03-25

Applicant: Apple Inc.

Inventor： Prashant Jain ,  Brian P. Lilly ,  Mahnaz Sadoughi-Yarandi ,  Helen Huang

IPC: G06F1/32

CPC classification number: G06F1/3275 ,  G06F1/3225 ,  G06F1/3296 ,  G06F12/0802 ,  G06F12/0846 ,  G06F12/0864 ,  G06F2212/1028 ,  G06F2212/502 ,  G06F2212/601 ,  G11C5/14 ,  G11C7/04 ,  G11C7/12 ,  G11C2207/2227 ,  Y02D10/13 ,  Y02D10/14 ,  Y02D10/172 ,  Y02D50/20

Abstract: Systems and methods for reducing leakage power in a L2 cache within a SoC. The L2 cache is partitioned into multiple banks, and each bank has its own separate power supply. An idle counter is maintained for each bank to count a number of cycles during which the bank has been inactive. The temperature and leaky factor of the SoC are used to select an operating point of the SoC. Based on the operating point, an idle counter threshold is set, with a high temperature and high leaky factor corresponding to a relatively low idle counter threshold, and with a low temperature and low leaky factor corresponding to a relatively high idle counter threshold. When a given idle counter exceeds the idle counter threshold, the voltage supplied to the corresponding bank is reduced to a voltage sufficient for retention of data but not for access.

Abstract translation: 降低SoC内二级缓存中漏电功率的系统和方法。 L2缓存分为多个银行，每个银行都有自己独立的电源。 为每个银行维护一个空闲计数器来计算银行已经不活动的周期数。 SoC的温度和泄漏因子用于选择SoC的工作点。 基于操作点，设置空闲计数器阈值，具有对应于相对低的空闲计数器阈值的高温度和高泄漏因子，以及对应于相对高的空闲计数器阈值的低温度和低泄漏因子。 当给定的空闲计数器超过空闲计数器阈值时，提供给相应存储体的电压降低到足以保留数据但不能访问的电压。