公开(公告)号：US09176879B2

公开(公告)日：2015-11-03

申请号：US13946327

申请日：2013-07-19

Applicant: Apple Inc.

Inventor： Brian P. Lilly ,  Gerard R. Williams, III ,  Mahnaz Sadoughi-Yarandi ,  Perumal R. Subramonium ,  Hari S. Kannan ,  Prashant Jain

IPC: G06F12/08 ,  G06F12/12

CPC classification number: G06F12/123 ,  G06F12/0862 ,  G06F12/0897 ,  G06F12/127 ,  G06F2212/1021

Abstract: A mechanism for evicting a cache line from a cache memory includes first selecting for eviction a least recently used cache line of a group of invalid cache lines. If all cache lines are valid, selecting for eviction a least recently used cache line of a group of cache lines in which no cache line of the group of cache lines is also stored within a higher level cache memory such as the L1 cache, for example. Lastly, if all cache lines are valid and there are no non-inclusive cache lines, selecting for eviction the least recently used cache line stored in the cache memory.

Abstract translation: 用于从高速缓冲存储器中逐出高速缓存行的机制包括首先选择驱逐一组无效高速缓存行的最近最少使用的高速缓存行。 如果所有高速缓存行都有效，则选择驱逐，一组高速缓存行的最近最少使用的高速缓存行，其中该高速缓存行组中的高速缓存行也不存储在诸如L1高速缓存的更高级高速缓冲存储器中 。 最后，如果所有高速缓存行都是有效的，并且没有非包含的高速缓存行，则选择驱逐存储在高速缓冲存储器中的最近最少使用的高速缓存行。

公开(公告)号：US09529730B2

公开(公告)日：2016-12-27

申请号：US14263386

申请日：2014-04-28

Applicant: Apple Inc.

Inventor： Mahnaz Sadoughi-Yarandi ,  Perumal R. Subramonium ,  Brian P. Lilly ,  Hari S. Kannan

IPC: G06F12/12

CPC classification number: G06F12/122 ,  G06F2212/1021 ,  G06F2212/1024 ,  G06F2212/1041

Abstract: A method and apparatus for evicting cache lines from a cache memory includes receiving a request from one of a plurality of processors. The cache memory is configured to store a plurality of cache lines, and a given cache line includes an identifier indicating a processor that performed a most recent access of the given cache line. The method further includes selecting a cache line for eviction from a group of least recently used cache lines, where each cache line of the group of least recently used cache lines occupy a priority position less that a predetermined value, and then evicting the selected cache line.

Abstract translation: 用于从高速缓冲存储器中取出高速缓存行的方法和装置包括从多个处理器之一接收请求。 高速缓存存储器被配置为存储多条高速缓存行，并且给定的高速缓存行包括指示执行给定高速缓存行的最近访问的处理器的标识符。 该方法还包括从一组最近最少使用的高速缓存行中选择用于逐出的高速缓存行，其中最近最少使用的高速缓存行的组中的每个高速缓存行占据优先级位置小于预定值，然后逐出所选择的高速缓存行 。

公开(公告)号：US20150309939A1

公开(公告)日：2015-10-29

申请号：US14263369

申请日：2014-04-28

Applicant: Apple Inc.

Inventor： Mahnaz Sadoughi-Yarandi ,  Perumal R. Subramonium ,  Brian P. Lilly ,  Hari S. Kannan

IPC: G06F12/08

CPC classification number: G06F12/0895 ,  G06F2212/1028 ,  Y02D10/13

Abstract: A method and apparatus for selectively powering down a portion of a cache memory includes determining a power down condition dependent upon a number of accesses to the cache memory. In response to the detection of the power down condition, selecting a group of cache ways included in the cache memory dependent upon a number of cache lines in each cache way that are also included in another cache memory. The method further includes locking and flushing the selected group of cache ways, and then activating a low power mode for the selected group of cache ways.

Abstract translation: 用于选择性地降低高速缓存存储器的一部分的方法和装置包括根据对高速缓冲存储器的访问次数确定掉电条件。 响应于断电状态的检测，根据还包括在另一个高速缓冲存储器中的每种高速缓存方式中的高速缓存行数量，选择包括在高速缓冲存储器中的一组高速缓存路。 该方法还包括锁定和刷新所选择的一组高速缓存路径，然后激活所选择的高速缓存路径组的低功率模式。

公开(公告)号：US09563575B2

公开(公告)日：2017-02-07

申请号：US14929645

申请日：2015-11-02

Applicant: Apple Inc.

Inventor： Brian P. Lilly ,  Gerard R. Williams, III ,  Mahnaz Sadoughi-Yarandi ,  Perumal R. Subramonium ,  Hari S. Kannan ,  Prashant Jain

IPC: G06F12/08 ,  G06F12/12

CPC classification number: G06F12/123 ,  G06F12/0862 ,  G06F12/0897 ,  G06F12/127 ,  G06F2212/1021

Abstract: A mechanism for evicting a cache line from a cache memory includes first selecting for eviction a least recently used cache line of a group of invalid cache lines. If all cache lines are valid, selecting for eviction a least recently used cache line of a group of cache lines in which no cache line of the group of cache lines is also stored within a higher level cache memory such as the L1 cache, for example. Lastly, if all cache lines are valid and there are no non-inclusive cache lines, selecting for eviction the least recently used cache line stored in the cache memory.

Abstract translation: 用于从高速缓冲存储器中逐出高速缓存行的机制包括首先选择驱逐一组无效高速缓存行的最近最少使用的高速缓存行。 如果所有高速缓存行都有效，则选择驱逐，一组高速缓存行的最近最少使用的高速缓存行，其中该高速缓存行组中的高速缓存行也不存储在诸如L1高速缓存的更高级高速缓冲存储器中 。 最后，如果所有高速缓存行都是有效的，并且没有非包含的高速缓存行，则选择驱逐存储在高速缓冲存储器中的最近最少使用的高速缓存行。

公开(公告)号：US09563567B2

公开(公告)日：2017-02-07

申请号：US14263369

申请日：2014-04-28

Applicant: Apple Inc.

Inventor： Mahnaz P Sadoughi-Yarandi ,  Perumal R. Subramonium ,  Brian P. Lilly ,  Hari S Kannan

IPC: G06F12/08

CPC classification number: G06F12/0895 ,  G06F2212/1028 ,  Y02D10/13

Abstract: A method and apparatus for selectively powering down a portion of a cache memory includes determining a power down condition dependent upon a number of accesses to the cache memory. In response to the detection of the power down condition, selecting a group of cache ways included in the cache memory dependent upon a number of cache lines in each cache way that are also included in another cache memory. The method further includes locking and flushing the selected group of cache ways, and then activating a low power mode for the selected group of cache ways.

Abstract translation: 用于选择性地降低高速缓存存储器的一部分的方法和装置包括根据对高速缓冲存储器的访问次数确定掉电条件。 响应于断电状态的检测，根据还包括在另一个高速缓冲存储器中的每种高速缓存方式中的高速缓存行数量，选择包括在高速缓冲存储器中的一组高速缓存路。 该方法还包括锁定和刷新所选择的一组高速缓存路径，然后激活所选择的高速缓存路径组的低功率模式。

公开(公告)号：US20160055099A1

公开(公告)日：2016-02-25

申请号：US14929645

申请日：2015-11-02

Applicant: Apple Inc.

Inventor： Brian P. Lilly ,  Gerard R. Williams, III ,  Mahnaz Sadoughi-Yarandi ,  Perumal R. Subramonium ,  Hari S. Kannan ,  Prashant Jain

IPC: G06F12/12

CPC classification number: G06F12/123 ,  G06F12/0862 ,  G06F12/0897 ,  G06F12/127 ,  G06F2212/1021

Abstract: A mechanism for evicting a cache line from a cache memory includes first selecting for eviction a least recently used cache line of a group of invalid cache lines. If all cache lines are valid, selecting for eviction a least recently used cache line of a group of cache lines in which no cache line of the group of cache lines is also stored within a higher level cache memory such as the L1 cache, for example. Lastly, if all cache lines are valid and there are no non-inclusive cache lines, selecting for eviction the least recently used cache line stored in the cache memory.

公开(公告)号：US20150309944A1

公开(公告)日：2015-10-29

申请号：US14263386

申请日：2014-04-28

Applicant: Apple Inc.

Inventor： Mahnaz Sadoughi-Yarandi ,  Perumal R. Subramonium ,  Brian P. Lilly ,  Hari S. Kannan

IPC: G06F12/12

CPC classification number: G06F12/122 ,  G06F2212/1021 ,  G06F2212/1024 ,  G06F2212/1041

Abstract: A method and apparatus for evicting cache lines from a cache memory includes receiving a request from one of a plurality of processors. The cache memory is configured to store a plurality of cache lines, and a given cache line includes an identifier indicating a processor that performed a most recent access of the given cache line. The method further includes selecting a cache line for eviction from a group of least recently used cache lines, where each cache line of the group of least recently used cache lines occupy a priority position less that a predetermined value, and then evicting the selected cache line.

Abstract translation: 用于从高速缓冲存储器中取出高速缓存行的方法和装置包括从多个处理器之一接收请求。 高速缓存存储器被配置为存储多条高速缓存行，并且给定的高速缓存行包括指示执行给定高速缓存行的最近访问的处理器的标识符。 该方法还包括从一组最近最少使用的高速缓存行中选择用于逐出的高速缓存行，其中最近最少使用的高速缓存行的组中的每个高速缓存行占据优先级位置小于预定值，然后逐出所选择的高速缓存行 。

公开(公告)号：US20150026404A1

公开(公告)日：2015-01-22

申请号：US13946327

申请日：2013-07-19

Applicant: Apple Inc.

Inventor： Brian P. Lilly ,  Gerard R. Williams, III ,  Mahnaz Sadoughi-Yarandi ,  Perumal R. Subramonium ,  Hari S. Kannan ,  Prashant Jain

IPC: G06F12/08

CPC classification number: G06F12/123 ,  G06F12/0862 ,  G06F12/0897 ,  G06F12/127 ,  G06F2212/1021

Abstract: A mechanism for evicting a cache line from a cache memory includes first selecting for eviction a least recently used cache line of a group of invalid cache lines. If all cache lines are valid, selecting for eviction a least recently used cache line of a group of cache lines in which no cache line of the group of cache lines is also stored within a higher level cache memory such as the L1 cache, for example. Lastly, if all cache lines are valid and there are no non-inclusive cache lines, selecting for eviction the least recently used cache line stored in the cache memory.

Abstract translation: 用于从高速缓冲存储器中逐出高速缓存行的机制包括首先选择驱逐一组无效高速缓存行的最近最少使用的高速缓存行。 如果所有高速缓存行都有效，则选择驱逐，一组高速缓存行的最近最少使用的高速缓存行，其中该高速缓存行组中的高速缓存行也不存储在诸如L1高速缓存的更高级高速缓冲存储器中 。 最后，如果所有高速缓存行都是有效的，并且没有非包含的高速缓存行，则选择驱逐存储在高速缓冲存储器中的最近最少使用的高速缓存行。