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    Refraction algorithm for production systems with content addressable memory
    1.
    发明授权
    Refraction algorithm for production systems with content addressable memory 失效

    公开(公告)号：US5579441A

    公开(公告)日：1996-11-26

    申请号：US290628

    申请日：1994-08-15

    申请人： John D. Bezek ,  Peter M. Kogge

    发明人： John D. Bezek ,  Peter M. Kogge

    IPC分类号： G06F9/46 ,  G06F9/44 ,  G06F15/16 ,  G06F15/167 ,  G06F15/173 ,  G06F15/80 ,  G06N5/04 ,  G06F17/00

    CPC分类号： G06N5/046

    摘要： An array processor system is provided with a system to implement a refraction algorithm to prevent incorrect expert system rule firing based on stale or future data, in those production system expert systems which employ content addressable memories for storage of the expert system's facts and its processing control information. The computer system is especially suitable for system which have expert system resources, and there are generic applications of refraction which can be used in any architecture, from scalar to massively parallel, and an associative memory or content addressable memory. The system need not use the RETE algorithm. The computer expert system, has an inference engine and a refraction check mechanism. It is provided with a time stamping mechanism. The computer memory will have working memory elements associated with the processing elements of the array processor. The array processor has a content addressable memory. A knowledge base is stored in the computer memory, and this base can be distributed among processing elements or pickets of the system. Each processing element or picket will have memory directly or indirectly associated with the processing element. The time stamping mechanism will order and identify the working memory elements. The computer program which forms the basis for the inferencing process controller system has controls which work with the operations of rules provided for examination of information in the system representing facts. The inferencing process contains the constraints which are subject to refraction checking. The refraction check system prevents the rule from subsequent firings on stale data. The refraction check prevents a rule from firing using data asserted into the inferencing system at a time later than the rule was selected for evaluation by the inferencing process. With the expert system resources the computer system instruction processing unit uses the content addressable memory provided by the memory store working memory elements to store the knowledge base.

    Inferencing production control computer system
    2.
    发明授权
    Inferencing production control computer system 失效
    推算生产控制计算机系统

    公开(公告)号：US5517642A

    公开(公告)日：1996-05-14

    申请号：US355948

    申请日：1994-12-14

    申请人： John D. Bezek ,  Peter M. Kogge

    发明人： John D. Bezek ,  Peter M. Kogge

    IPC分类号： F02B75/02 ,  G06F7/57 ,  G06F9/30 ,  G06F9/318 ,  G06F9/38 ,  G06F15/173 ,  G06F15/80 ,  G06N5/04 ,  G06F15/18

    CPC分类号： G06F15/17337 ,  G06F15/17343 ,  G06F15/17368 ,  G06F15/17381 ,  G06F15/8007 ,  G06F15/8015 ,  G06F15/803 ,  G06F7/483 ,  G06N5/046 ,  F02B2075/027 ,  Y10S707/99933

    摘要： A computer system, and its parallel and serial implementations, its serial and parallel network and multi-processor configurations, with tight and loose coupling among processors. The computer system has a CAM coupled to the computer system or imbedded therein. CAM requests may be processed serially, or as parallel queries and coupled with PAPS (Parallel Associative Processor System) capabilities (P-CAM). The computer system may be configured as an expert system preferably having combined tuple space (TS) and CAM (content addressable memory) resources, an inference engine and a knowledge base. As an expert system, improvements for production processing are provided which surpass prior art performance represented by RETE and CLIPS. An inferencing process for production systems is disclosed, and a process for working memory element assertions. The computer system is provided with a language construct which is language independent in the form of a sub-set paradigm having three basic operators and three basic extensions. The basic primitive sub-set paradigm including OUT( ); IN( ) and READ( ). Extensions of said basic sub-set are Sample( ); SampleList( ); and ReadList( ). These primitives may be used with LINDA, and with various compilers. EVAL of LINDA is not used but instead the sub-set paradigm is used with CAM for tuple space operations in data base applications. The language construct paradigm is use to envelope and control CAM operations.

    摘要翻译： 计算机系统及其并行和串行实现，其串行和并行网络和多处理器配置，处理器之间的紧耦合和松散耦合。 计算机系统具有耦合到计算机系统或嵌入其中的CAM。 CAM请求可以串行处理，也可以作为并行查询，并与PAPS（并行关联处理器系统）功能（P-CAM）相结合。 计算机系统可以被配置为优选地具有组合元组空间（TS）和CAM（内容可寻址存储器）资源，推理机和知识库的专家系统。 作为专家系统，提供了超越RETE和CLIPS代表的现有技术性能的生产处理方面的改进。 公开了生产系统的推理过程，以及用于处理存储器元件断言的过程。 计算机系统具有语言独立的语言结构，其具有具有三个基本操作符和三个基本扩展的子集范例的形式。 包括OUT（）的基本原语子集范例; IN（）和READ（）。 所述基本子集的扩展是Sample（）; SampleList（）; 和ReadList（）。 这些原语可以与LINDA和各种编译器一起使用。 不使用LINDA的EVAL，而是使用子集范例与CAM一起用于数据库应用程序中的元组空间操作。 语言构建范例用于包络和控制CAM操作。

    Dynamic multi-mode parallel processing array
    3.
    发明授权
    Dynamic multi-mode parallel processing array 失效
    动态多模并行处理阵列

    公开(公告)号：US5475856A

    公开(公告)日：1995-12-12

    申请号：US324295

    申请日：1994-10-17

    申请人： Peter M. Kogge

    发明人： Peter M. Kogge

    IPC分类号： G06F15/16 ,  F02B75/02 ,  G06F7/57 ,  G06F9/30 ,  G06F9/318 ,  G06F9/38 ,  G06F15/173 ,  G06F15/80 ,  G06F13/00

    CPC分类号： G06F9/3891 ,  G06F15/17337 ,  G06F15/17343 ,  G06F15/17368 ,  G06F15/17381 ,  G06F15/8007 ,  G06F15/8015 ,  G06F15/803 ,  G06F7/483 ,  G06F9/30 ,  G06F9/30036 ,  G06F9/30145 ,  G06F9/30167 ,  G06F9/3017 ,  G06F9/30189 ,  G06F9/38 ,  G06F9/3802 ,  G06F9/3834 ,  G06F9/3836 ,  G06F9/3851 ,  G06F9/3885 ,  G06F9/3887 ,  G06F9/3889 ,  F02B2075/027

    摘要： A Parallel RISC computer system is provided by a multi-mode dynamic multi-mode parallel processor array with one embodiment illustrating a tightly coupled VLSI embodiment with an architecture which can be extended to more widely placed processing elements through the interconnection network which couples multiple processors capable of MIMD mode processing to one another with broadcast of instructions to selected groups of units controlled by a controlling processor. The coupling of the processing elements logic enables dynamic mode assignment and dynamic mode switching, allowing processors operating in a SIMD mode to make maximum memory and cycle time usage. On and instruction by instruction level basis, modes can be switched from SIMD to MIMD, and even into SISD mode on the controlling processor for inherently sequential computation allowing a programmer or complier to build a program for the computer system which uses the optimal kind of parallelism (SISD, SIMD, MIMD). Furthermore, this execution, particularly in the SIMD mode, can be set up for running applications at the limit of memory cycle time. With the ALLNODE switch and alternatives paths a system can be dynamically achieved in a few cycles for many many processors. Each processing element and memory and has MIMD capability the processor's an instruction register, condition register and program counter provide common resources which are used in MIMD and SIMD. The program counter become a base register in SIMD mode.

    摘要翻译： 并行RISC计算机系统由多模式动态多模式并行处理器阵列提供，其中一个实施例示出了具有结构的紧密耦合的VLSI实施例，该架构可以通过互连网络扩展到更广泛放置的处理元件，该互连网络将多个处理器 通过向由控制处理器控制的所选择的单元组广播指令而将MIMD模式处理彼此广播。 处理元件逻辑的耦合使得能够进行动态模式分配和动态模式切换，使得以SIMD模式操作的处理器能够实现最大的存储器和周期时间使用。 通过指令级别进行指令，模式可以从SIMD切换到MIMD，甚至可以在控制处理器上进行SISD模式，用于固有顺序计算，允许程序员或编译器为使用最佳并行性的计算机系统构建程序 （SISD，SIMD，MIMD）。 此外，特别是在SIMD模式下的这种执行可以在存储周期时间的限制下设置运行应用程序。 使用ALLNODE开关和替代路径，可以在许多处理器的几个周期内动态实现系统。 每个处理元件和存储器具有MIMD能力，处理器的指令寄存器，条件寄存器和程序计数器提供MIMD和SIMD中使用的公共资源。 程序计数器成为SIMD模式下的基址寄存器。

    Interconnect topology with reduced implementation requirements
    4.
    发明授权
    Interconnect topology with reduced implementation requirements 有权
    互连拓扑结构与实现要求降低

    公开(公告)号：US09106440B2

    公开(公告)日：2015-08-11

    申请号：US13585410

    申请日：2012-08-14

    申请人： Peter M. Kogge

    发明人： Peter M. Kogge

    IPC分类号： H04L12/28 ,  H04L12/42 ,  H04L12/721 ,  H04L12/751 ,  H04L12/753

    CPC分类号： H04L12/42 ,  H04L45/02 ,  H04L45/06 ,  H04L45/48

    摘要： A topology for routing message traffic between interconnecting nodes of a network is provided that includes a plurality of rings having a plurality of interconnecting nodes. A number of trees include at least one leaf at a same relative position of the rings. The trees and the rings form a unique combination that provides superior network performance for moderate numbers of the interconnecting nodes, wherein each interconnecting node has only a limited ability to handle a plurality of links.

    摘要翻译： 提供了一种用于在网络的互连节点之间路由消息业务的拓扑，其包括具有多个互连节点的多个环。 许多树包括在环的相同相对位置处的至少一个叶。 树和环形成独特的组合，其为中等数量的互连节点提供优异的网络性能，其中每个互连节点仅具有处理多个链路的有限能力。

    Architectures for self-contained, mobile, memory programming
    7.
    发明授权
    Architectures for self-contained, mobile, memory programming 有权
    独立的，移动的，内存编程的架构

    公开(公告)号：US07185150B1

    公开(公告)日：2007-02-27

    申请号：US10665263

    申请日：2003-09-22

    申请人： Peter M. Kogge

    发明人： Peter M. Kogge

    IPC分类号： G06F12/00 ,  G06F9/00

    CPC分类号： G06F9/5016 ,  G06F9/3009

    摘要： A computer system comprising: a plurality of memories each containing one or more locations; and a first threadlet for causing a first program to run in the computer system when at least one first memory location of the plurality of memory locations is local to the threadlet. Also provided is a method allowing such a threadlet to move itself to memories that include some specified second memory location.

    摘要翻译： 一种计算机系统，包括：多个存储器，每个存储器包含一个或多个位置; 以及当所述多个存储器位置中的至少一个第一存储器位置是所述线程的本地时，用于使得第一程序在所述计算机系统中运行的第一线程。 还提供了允许这样的线程将自身移动到包括一些指定的第二存储器位置的存储器的方法。

    Dual priority switching apparatus for simplex networks
    8.
    发明授权
    Dual priority switching apparatus for simplex networks 失效
    用于单工网络的双重优先切换装置

    公开(公告)号：US5444705A

    公开(公告)日：1995-08-22

    申请号：US800652

    申请日：1991-11-27

    申请人： Howard T. Olnowich ,  Thomas N. Barker ,  Peter M. Kogge ,  Gilbert C. Vandling, III

    发明人： Howard T. Olnowich ,  Thomas N. Barker ,  Peter M. Kogge ,  Gilbert C. Vandling, III

    IPC分类号： G06F11/26 ,  G06F13/364 ,  G06F13/40 ,  G06F15/173 ,  H03M9/00 ,  H04L1/00 ,  H04L7/033 ,  H04L7/04 ,  H04L12/18 ,  H04L12/56 ,  H04Q11/00 ,  H04Q11/04 ,  H04J3/02

    CPC分类号： H04L1/0057 ,  G06F13/364 ,  G06F13/4022 ,  G06F15/17375 ,  G06F15/17393 ,  H03M9/00 ,  H04L49/205 ,  H04L7/0338 ,  H04L7/044 ,  H04Q11/0478 ,  G06F11/261 ,  H04L49/101 ,  H04L49/1515 ,  H04L49/1523 ,  H04L49/201 ,  H04L49/40 ,  H04L49/55 ,  H04Q11/0066

    摘要： A high priority path is added to the normal low priority path through a multi-stage switching network. The high priority path is established at the quickest possible speed because the high priority command is stored at the switch stage involved and made on a priority basis as soon as an output port becomes available. In addition, a positive feedback is given to the node establishing the connection immediately upon the making of the connection so that it may proceed at the earliest possible moment. The high priority path is capable of processing multiple high priority pending requests, and resolving the high priority contention using a snapshot register which implements a rotating priority such that no one requesting device can ever be locked out or experience data starvation. A dual priority switching apparatus with input port connections to output port connections uses as asynchronous means to resolve contention under low priority and the absence of blockage conditions, and switches automatically to a priority driven synchronous means of resolving contention. The protocol requires several parallel data lines plus four control lines so that the switching apparatus can be used for networks having a plurality of nodes, each node having a plurality of input and output ports, with a multiplexer control circuit for each output port for connecting any of I inputs to any of Z outputs, where I and Z can assume any unique value greater or equal to two. The switch has a single physical network path element over which either a low priority or high priority path can be established.

    摘要翻译： 通过多级交换网络将高优先级路径添加到正常的低优先级路径。 高优先级路径以最快的速度建立，因为高优先级命令存储在所涉及的切换阶段，并且一旦输出端口变得可用就在优先级基础上进行。 另外，在建立连接时立即建立连接的节点，使得它可以在尽可能早的时刻进行肯定的反馈。 高优先级路径能够处理多个高优先级待处理请求，并且使用实现旋转优先级的快照寄存器来解决高优先权争用，使得没有一个请求设备可以被锁定或经历数据不足。 具有与输出端口连接的输入端口连接的双重优先级交换设备使用作为异步方式来在低优先级和无阻塞条件下解决争用，并且自动切换到解决争用的优先级驱动的同步装置。 该协议需要几条并行数据线加上四条控制线，使得交换设备可用于具有多个节点的网络，每个节点具有多个输入和输出端口，每个输出端口具有多路复用器控制电路，用于连接任何 的I输入到任何Z输出，其中I和Z可以采用大于或等于2的任何唯一值。 交换机具有单个物理网络路径元素，通过该单个物理网络路径元素可以建立低优先级或高优先级路径。

    Response time detection in a network having shared interfaces
    9.
    发明授权
    Response time detection in a network having shared interfaces 有权
    具有共享接口的网络中的响应时间检测

    公开(公告)号：US07639628B2

    公开(公告)日：2009-12-29

    申请号：US11457543

    申请日：2006-07-14

    申请人： Peter M. Kogge

    发明人： Peter M. Kogge

    IPC分类号： G08C15/00

    CPC分类号： H04L43/0852

    摘要： A method that includes activating and deactivating two counts between an active state and not an active state such that no more than one count at a time is in an active state. The method also includes receiving a request packet of information that requires a reply and incrementing the count that is in an active state, and setting a flag in the request packet of information that requires a reply, the flag being set to correspond to the count that is in the active state. The method further includes receiving a reply packet of information corresponding to a previously received request packet of information, the reply packet of information having a flag setting corresponding to the previously received request packet of information, and decrementing the count that corresponds to the flag setting of the reply packet of information. A network is also disclosed.

    摘要翻译： 一种方法，其包括激活和去激活活动状态而不是活动状态之间的两个计数，使得一次不超过一个计数处于活动状态。 该方法还包括接收需要回复并递增处于活动状态的计数的信息的请求分组，以及在需要回复的信息的请求分组中设置标志，该标志被设置为对应于 处于活跃状态。 该方法还包括接收与先前接收到的信息的请求分组对应的信息的应答分组，该信息的应答分组具有与先前接收到的信息请求分组对应的标志设置，并且减少对应于标志设置的计数 回复信息包。 还公开了网络。

    Array processor dotted communication network based on H-DOTs
    10.
    发明授权
    Array processor dotted communication network based on H-DOTs 失效
    基于H-DOT的阵列处理器虚拟通信网络

    公开(公告)号：US5630162A

    公开(公告)日：1997-05-13

    申请号：US430708

    申请日：1995-04-27

    申请人： Paul A. Wilkinson ,  Peter M. Kogge

    发明人： Paul A. Wilkinson ,  Peter M. Kogge

    IPC分类号： G06F7/57 ,  G06F9/30 ,  G06F9/318 ,  G06F9/38 ,  G06F15/173 ,  G06F15/80 ,  G06F15/16

    CPC分类号： G06F15/17337 ,  G06F15/17343 ,  G06F15/17381 ,  G06F15/8007 ,  G06F15/8023 ,  G06F7/483 ,  G06F9/30036 ,  G06F9/3887

    摘要： A parallel processor array of the SIMD or MIMD type requires a highly organized communication network for communication between processing elements (PEs). For a communication network a dotted network structure is created which reduces the magnitude of the the networking implementation using a link with two vertical paths and two horizontal paths for a single link, denominated H-DOT. A significant result of the H-DOT network configuration is that it applies to several topologies, and furthermore, the array of processors can generally be extended in size and in additional dimensions while retaining the basic two port array processing element. Both synchronous and routed control can be included. Routing algorithm routines are discussed. The network configuration can be used in massively parallel processors or other smaller array processors which can implement SIMD and MIMD processes.

    摘要翻译： SIMD或MIMD类型的并行处理器阵列需要用于处理元件（PE）之间的通信的高度组织的通信网络。 对于通信网络，创建了虚拟网络结构，其使用具有命名为H-DOT的单个链路的两个垂直路径和两个水平路径的链路来减小网络实施的大小。 H-DOT网络配置的一个重要结果是它适用于多个拓扑，此外，处理器阵列通常可以在大小和额外的维度上进行扩展，同时保留基本的两端口阵列处理元件。 可以包括同步和路由控制。 讨论路由算法例程。 网络配置可用于大规模并行处理器或其他可实现SIMD和MIMD过程的较小阵列处理器。