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    Array processor dotted communication network based on H-DOTs
    1.
    发明授权
    Array processor dotted communication network based on H-DOTs 失效
    基于H-DOT的阵列处理器虚拟通信网络

    公开(公告)号：US5630162A

    公开(公告)日：1997-05-13

    申请号：US430708

    申请日：1995-04-27

    申请人： Paul A. Wilkinson ,  Peter M. Kogge

    发明人： Paul A. Wilkinson ,  Peter M. Kogge

    IPC分类号： G06F7/57 ,  G06F9/30 ,  G06F9/318 ,  G06F9/38 ,  G06F15/173 ,  G06F15/80 ,  G06F15/16

    CPC分类号： G06F15/17337 ,  G06F15/17343 ,  G06F15/17381 ,  G06F15/8007 ,  G06F15/8023 ,  G06F7/483 ,  G06F9/30036 ,  G06F9/3887

    摘要： A parallel processor array of the SIMD or MIMD type requires a highly organized communication network for communication between processing elements (PEs). For a communication network a dotted network structure is created which reduces the magnitude of the the networking implementation using a link with two vertical paths and two horizontal paths for a single link, denominated H-DOT. A significant result of the H-DOT network configuration is that it applies to several topologies, and furthermore, the array of processors can generally be extended in size and in additional dimensions while retaining the basic two port array processing element. Both synchronous and routed control can be included. Routing algorithm routines are discussed. The network configuration can be used in massively parallel processors or other smaller array processors which can implement SIMD and MIMD processes.

    摘要翻译： SIMD或MIMD类型的并行处理器阵列需要用于处理元件（PE）之间的通信的高度组织的通信网络。 对于通信网络，创建了虚拟网络结构，其使用具有命名为H-DOT的单个链路的两个垂直路径和两个水平路径的链路来减小网络实施的大小。 H-DOT网络配置的一个重要结果是它适用于多个拓扑，此外，处理器阵列通常可以在大小和额外的维度上进行扩展，同时保留基本的两端口阵列处理元件。 可以包括同步和路由控制。 讨论路由算法例程。 网络配置可用于大规模并行处理器或其他可实现SIMD和MIMD过程的较小阵列处理器。

    Refraction algorithm for production systems with content addressable memory
    3.
    发明授权
    Refraction algorithm for production systems with content addressable memory 失效

    公开(公告)号：US5579441A

    公开(公告)日：1996-11-26

    申请号：US290628

    申请日：1994-08-15

    申请人： John D. Bezek ,  Peter M. Kogge

    发明人： John D. Bezek ,  Peter M. Kogge

    IPC分类号： G06F9/46 ,  G06F9/44 ,  G06F15/16 ,  G06F15/167 ,  G06F15/173 ,  G06F15/80 ,  G06N5/04 ,  G06F17/00

    CPC分类号： G06N5/046

    摘要： An array processor system is provided with a system to implement a refraction algorithm to prevent incorrect expert system rule firing based on stale or future data, in those production system expert systems which employ content addressable memories for storage of the expert system's facts and its processing control information. The computer system is especially suitable for system which have expert system resources, and there are generic applications of refraction which can be used in any architecture, from scalar to massively parallel, and an associative memory or content addressable memory. The system need not use the RETE algorithm. The computer expert system, has an inference engine and a refraction check mechanism. It is provided with a time stamping mechanism. The computer memory will have working memory elements associated with the processing elements of the array processor. The array processor has a content addressable memory. A knowledge base is stored in the computer memory, and this base can be distributed among processing elements or pickets of the system. Each processing element or picket will have memory directly or indirectly associated with the processing element. The time stamping mechanism will order and identify the working memory elements. The computer program which forms the basis for the inferencing process controller system has controls which work with the operations of rules provided for examination of information in the system representing facts. The inferencing process contains the constraints which are subject to refraction checking. The refraction check system prevents the rule from subsequent firings on stale data. The refraction check prevents a rule from firing using data asserted into the inferencing system at a time later than the rule was selected for evaluation by the inferencing process. With the expert system resources the computer system instruction processing unit uses the content addressable memory provided by the memory store working memory elements to store the knowledge base.

    Inferencing production control computer system
    4.
    发明授权
    Inferencing production control computer system 失效
    推算生产控制计算机系统

    公开(公告)号：US5517642A

    公开(公告)日：1996-05-14

    申请号：US355948

    申请日：1994-12-14

    申请人： John D. Bezek ,  Peter M. Kogge

    发明人： John D. Bezek ,  Peter M. Kogge

    IPC分类号： F02B75/02 ,  G06F7/57 ,  G06F9/30 ,  G06F9/318 ,  G06F9/38 ,  G06F15/173 ,  G06F15/80 ,  G06N5/04 ,  G06F15/18

    CPC分类号： G06F15/17337 ,  G06F15/17343 ,  G06F15/17368 ,  G06F15/17381 ,  G06F15/8007 ,  G06F15/8015 ,  G06F15/803 ,  G06F7/483 ,  G06N5/046 ,  F02B2075/027 ,  Y10S707/99933

    摘要： A computer system, and its parallel and serial implementations, its serial and parallel network and multi-processor configurations, with tight and loose coupling among processors. The computer system has a CAM coupled to the computer system or imbedded therein. CAM requests may be processed serially, or as parallel queries and coupled with PAPS (Parallel Associative Processor System) capabilities (P-CAM). The computer system may be configured as an expert system preferably having combined tuple space (TS) and CAM (content addressable memory) resources, an inference engine and a knowledge base. As an expert system, improvements for production processing are provided which surpass prior art performance represented by RETE and CLIPS. An inferencing process for production systems is disclosed, and a process for working memory element assertions. The computer system is provided with a language construct which is language independent in the form of a sub-set paradigm having three basic operators and three basic extensions. The basic primitive sub-set paradigm including OUT( ); IN( ) and READ( ). Extensions of said basic sub-set are Sample( ); SampleList( ); and ReadList( ). These primitives may be used with LINDA, and with various compilers. EVAL of LINDA is not used but instead the sub-set paradigm is used with CAM for tuple space operations in data base applications. The language construct paradigm is use to envelope and control CAM operations.

    摘要翻译： 计算机系统及其并行和串行实现，其串行和并行网络和多处理器配置，处理器之间的紧耦合和松散耦合。 计算机系统具有耦合到计算机系统或嵌入其中的CAM。 CAM请求可以串行处理，也可以作为并行查询，并与PAPS（并行关联处理器系统）功能（P-CAM）相结合。 计算机系统可以被配置为优选地具有组合元组空间（TS）和CAM（内容可寻址存储器）资源，推理机和知识库的专家系统。 作为专家系统，提供了超越RETE和CLIPS代表的现有技术性能的生产处理方面的改进。 公开了生产系统的推理过程，以及用于处理存储器元件断言的过程。 计算机系统具有语言独立的语言结构，其具有具有三个基本操作符和三个基本扩展的子集范例的形式。 包括OUT（）的基本原语子集范例; IN（）和READ（）。 所述基本子集的扩展是Sample（）; SampleList（）; 和ReadList（）。 这些原语可以与LINDA和各种编译器一起使用。 不使用LINDA的EVAL，而是使用子集范例与CAM一起用于数据库应用程序中的元组空间操作。 语言构建范例用于包络和控制CAM操作。

    Dynamic multi-mode parallel processing array
    5.
    发明授权
    Dynamic multi-mode parallel processing array 失效
    动态多模并行处理阵列

    公开(公告)号：US5475856A

    公开(公告)日：1995-12-12

    申请号：US324295

    申请日：1994-10-17

    申请人： Peter M. Kogge

    发明人： Peter M. Kogge

    IPC分类号： G06F15/16 ,  F02B75/02 ,  G06F7/57 ,  G06F9/30 ,  G06F9/318 ,  G06F9/38 ,  G06F15/173 ,  G06F15/80 ,  G06F13/00

    CPC分类号： G06F9/3891 ,  G06F15/17337 ,  G06F15/17343 ,  G06F15/17368 ,  G06F15/17381 ,  G06F15/8007 ,  G06F15/8015 ,  G06F15/803 ,  G06F7/483 ,  G06F9/30 ,  G06F9/30036 ,  G06F9/30145 ,  G06F9/30167 ,  G06F9/3017 ,  G06F9/30189 ,  G06F9/38 ,  G06F9/3802 ,  G06F9/3834 ,  G06F9/3836 ,  G06F9/3851 ,  G06F9/3885 ,  G06F9/3887 ,  G06F9/3889 ,  F02B2075/027

    摘要： A Parallel RISC computer system is provided by a multi-mode dynamic multi-mode parallel processor array with one embodiment illustrating a tightly coupled VLSI embodiment with an architecture which can be extended to more widely placed processing elements through the interconnection network which couples multiple processors capable of MIMD mode processing to one another with broadcast of instructions to selected groups of units controlled by a controlling processor. The coupling of the processing elements logic enables dynamic mode assignment and dynamic mode switching, allowing processors operating in a SIMD mode to make maximum memory and cycle time usage. On and instruction by instruction level basis, modes can be switched from SIMD to MIMD, and even into SISD mode on the controlling processor for inherently sequential computation allowing a programmer or complier to build a program for the computer system which uses the optimal kind of parallelism (SISD, SIMD, MIMD). Furthermore, this execution, particularly in the SIMD mode, can be set up for running applications at the limit of memory cycle time. With the ALLNODE switch and alternatives paths a system can be dynamically achieved in a few cycles for many many processors. Each processing element and memory and has MIMD capability the processor's an instruction register, condition register and program counter provide common resources which are used in MIMD and SIMD. The program counter become a base register in SIMD mode.

    摘要翻译： 并行RISC计算机系统由多模式动态多模式并行处理器阵列提供，其中一个实施例示出了具有结构的紧密耦合的VLSI实施例，该架构可以通过互连网络扩展到更广泛放置的处理元件，该互连网络将多个处理器 通过向由控制处理器控制的所选择的单元组广播指令而将MIMD模式处理彼此广播。 处理元件逻辑的耦合使得能够进行动态模式分配和动态模式切换，使得以SIMD模式操作的处理器能够实现最大的存储器和周期时间使用。 通过指令级别进行指令，模式可以从SIMD切换到MIMD，甚至可以在控制处理器上进行SISD模式，用于固有顺序计算，允许程序员或编译器为使用最佳并行性的计算机系统构建程序 （SISD，SIMD，MIMD）。 此外，特别是在SIMD模式下的这种执行可以在存储周期时间的限制下设置运行应用程序。 使用ALLNODE开关和替代路径，可以在许多处理器的几个周期内动态实现系统。 每个处理元件和存储器具有MIMD能力，处理器的指令寄存器，条件寄存器和程序计数器提供MIMD和SIMD中使用的公共资源。 程序计数器成为SIMD模式下的基址寄存器。

    Response time detection in a network having shared interfaces
    6.
    发明授权
    Response time detection in a network having shared interfaces 有权
    具有共享接口的网络中的响应时间检测

    公开(公告)号：US07639628B2

    公开(公告)日：2009-12-29

    申请号：US11457543

    申请日：2006-07-14

    申请人： Peter M. Kogge

    发明人： Peter M. Kogge

    IPC分类号： G08C15/00

    CPC分类号： H04L43/0852

    摘要： A method that includes activating and deactivating two counts between an active state and not an active state such that no more than one count at a time is in an active state. The method also includes receiving a request packet of information that requires a reply and incrementing the count that is in an active state, and setting a flag in the request packet of information that requires a reply, the flag being set to correspond to the count that is in the active state. The method further includes receiving a reply packet of information corresponding to a previously received request packet of information, the reply packet of information having a flag setting corresponding to the previously received request packet of information, and decrementing the count that corresponds to the flag setting of the reply packet of information. A network is also disclosed.

    摘要翻译： 一种方法，其包括激活和去激活活动状态而不是活动状态之间的两个计数，使得一次不超过一个计数处于活动状态。 该方法还包括接收需要回复并递增处于活动状态的计数的信息的请求分组，以及在需要回复的信息的请求分组中设置标志，该标志被设置为对应于 处于活跃状态。 该方法还包括接收与先前接收到的信息的请求分组对应的信息的应答分组，该信息的应答分组具有与先前接收到的信息请求分组对应的标志设置，并且减少对应于标志设置的计数 回复信息包。 还公开了网络。

    Data processing system having prediction by using an embedded guess bit of remapped and compressed opcodes
    7.
    发明授权
    Data processing system having prediction by using an embedded guess bit of remapped and compressed opcodes 失效
    数据处理系统通过使用重映射和压缩操作码的嵌入猜测位进行预测

    公开(公告)号：US5463746A

    公开(公告)日：1995-10-31

    申请号：US968790

    申请日：1992-10-30

    申请人： Timothy B. Brodnax ,  Bryan K. Bullis ,  Steven A. King ,  Peter M. Kogge ,  Dale A. Rickard

    发明人： Timothy B. Brodnax ,  Bryan K. Bullis ,  Steven A. King ,  Peter M. Kogge ,  Dale A. Rickard

    IPC分类号： G06F9/30 ,  G06F9/38

    CPC分类号： G06F9/30178 ,  G06F9/30 ,  G06F9/3844

    摘要： A data processing system includes branch prediction apparatus for storing branch data in a branch prediction RAM after each branch has occurred. The RAM interfaces with branch logic means which tracks whether a branch is in progress and if a branch was guessed. An operational code compression means forms each instruction into a new operation code of lesser bits and embeds a guess bit into the new operational code. Control means decode the compressed operational code as an input to an instruction execution unit whereby conditional branch occurs based on the guess bit provided a branch instruction is not in progress in the system.

    摘要翻译： 数据处理系统包括分支预测装置，用于在每个分支发生之后在分支预测RAM中存储分支数据。 RAM与分支逻辑装置接口，跟踪分支是否正在进行，如果分支被猜测。 操作代码压缩装置将每个指令形成为较小位的新操作代码，并将猜测位嵌入到新的操作代码中。 控制装置将压缩的操作码解码为指令执行单元的输入，从而基于所提供的猜测位发生条件分支，系统中未进行分支指令。

    Skewed matrix address generator
    8.
    发明授权
    Skewed matrix address generator 失效
    倾斜矩阵地址发生器

    公开(公告)号：US4370732A

    公开(公告)日：1983-01-25

    申请号：US187256

    申请日：1980-09-15

    申请人： Peter M. Kogge

    发明人： Peter M. Kogge

    IPC分类号： G06F9/345 ,  G06F9/355 ,  G06F12/02 ,  G06F12/06 ,  G06F17/16 ,  G06F9/34

    CPC分类号： G06F9/3552 ,  G06F12/0207 ,  G06F9/345

    摘要： An address generator for an M-interleaved memory for accessing row or column elements of a matrix stored in a skewed matrix pattern includes an apparatus for circularly shifting the addresses for the i.sup.th row of a matrix by s(i-1) positions so that both row and column elements of the matrix can be accessed at the same access rate. In other words, apparatus is provided for circularly generating the sequences of appropriate memory addresses for the desired row or column elements so that either the row or column elements can be accessed at the memory system's maximum access rate. The apparatus includes a base register having an input connected to a first adder which adds an input value A to the contents in the base register for storing the output of the adder as a pointer to the beginning of the current row of the matrix in the memory to be accessed. The apparatus further includes an index register having an input connected to an adder for adding an input value B to the contents of the index register and that sum is conditionally added in a third adder to an input value C which sum is then stored in the index register for indicating which column element in the matrix is to be accessed. The apparatus further includes an adder having inputs connected to the base register and the index register for generating the skewed matrix address to be accessed. The resulting apparatus enables both row and column elements of the matrix to be accessed at substantially the same rate.

    摘要翻译： 用于访问存储在偏斜矩阵模式中的矩阵的行或列元素的M交错存储器的地址生成器包括用于将矩阵的第i行的地址循环移位s（i-1）位置的装置， 可以以相同的访问速率访问矩阵的行和列元素。 换句话说，提供了用于循环地产生用于所需行或列元素的适当存储器地址的序列的装置，使得可以以存储器系统的最大访问速率访问行或列元素。 该装置包括基本寄存器，其具有连接到第一加法器的输入端，该第一加法器将输入值A与基址寄存器中的内容相加，用于存储加法器的输出作为指向存储器中矩阵的当前行的开头的指针 被访问。 该装置还包括索引寄存器，该索引寄存器具有连接到加法器的输入端，用于将输入值B加到索引寄存器的内容，并且该和被有条件地相加于第三加法器中的输入值C，该输入值C将该和存储在索引中 用于指示矩阵中哪个列元素被访问的寄存器。 该装置还包括加法器，其具有连接到基址寄存器和索引寄存器的输入端，用于产生要访问的偏斜矩阵地址。 所得到的装置能够以基本上相同的速率访问矩阵的行和列元素。

    Interconnect topology with reduced implementation requirements
    9.
    发明授权
    Interconnect topology with reduced implementation requirements 有权
    互连拓扑结构与实现要求降低

    公开(公告)号：US09106440B2

    公开(公告)日：2015-08-11

    申请号：US13585410

    申请日：2012-08-14

    申请人： Peter M. Kogge

    发明人： Peter M. Kogge

    IPC分类号： H04L12/28 ,  H04L12/42 ,  H04L12/721 ,  H04L12/751 ,  H04L12/753

    CPC分类号： H04L12/42 ,  H04L45/02 ,  H04L45/06 ,  H04L45/48

    摘要： A topology for routing message traffic between interconnecting nodes of a network is provided that includes a plurality of rings having a plurality of interconnecting nodes. A number of trees include at least one leaf at a same relative position of the rings. The trees and the rings form a unique combination that provides superior network performance for moderate numbers of the interconnecting nodes, wherein each interconnecting node has only a limited ability to handle a plurality of links.

    摘要翻译： 提供了一种用于在网络的互连节点之间路由消息业务的拓扑，其包括具有多个互连节点的多个环。 许多树包括在环的相同相对位置处的至少一个叶。 树和环形成独特的组合，其为中等数量的互连节点提供优异的网络性能，其中每个互连节点仅具有处理多个链路的有限能力。