公开(公告)号：US08803216B2

公开(公告)日：2014-08-12

申请号：US11277008

申请日：2006-03-20

Applicant: Meng Ding ,  Lei Xue ,  Mark Randolph ,  Chi Chang ,  Robert Bertram Ogle, Jr.

Inventor： Meng Ding ,  Lei Xue ,  Mark Randolph ,  Chi Chang ,  Robert Bertram Ogle, Jr.

IPC: H01L29/788 ,  H01L27/115 ,  H01L21/28 ,  H01L29/792 ,  H01L29/51

CPC classification number: H01L21/28282 ,  H01L27/115 ,  H01L27/11568 ,  H01L29/513 ,  H01L29/7923

Abstract: A memory cell system including providing a substrate, forming a charge-storing stack having silicon-rich nitride on the substrate, and forming a gate on the charge-storing stack.

Abstract translation: 一种存储单元系统，包括提供衬底，在衬底上形成具有富含硅的氮化物的电荷存储堆叠，并在电荷存储堆上形成栅极。

公开(公告)号：US07750407B2

公开(公告)日：2010-07-06

申请号：US11612265

申请日：2006-12-18

Applicant: Wei Zheng ,  Jean Yang ,  Mark Randolph ,  Ming Kwan ,  Yi He ,  Zhizheng Liu ,  Meng Ding

Inventor： Wei Zheng ,  Jean Yang ,  Mark Randolph ,  Ming Kwan ,  Yi He ,  Zhizheng Liu ,  Meng Ding

IPC: H01L29/76

CPC classification number: H01L27/105 ,  H01L27/11526 ,  H01L27/11531

Abstract: A semiconductor device includes a substrate and a memory cell formed on the substrate. The memory cell includes a word line. The semiconductor device also includes a protection area formed in the substrate, a conductive structure configured to extend the word line to the protection area, and a contact configured to short the word line and the protection area.

Abstract translation: 半导体器件包括衬底和形成在衬底上的存储单元。 存储单元包括字线。 半导体器件还包括形成在衬底中的保护区域，被配置为将字线延伸到保护区域的导电结构以及被配置为使字线和保护区域短路的触点。

公开(公告)号：US20100027350A1

公开(公告)日：2010-02-04

申请号：US12557721

申请日：2009-09-11

Applicant: Ashot MELIK-MARTIROSIAN ,  Ed RUNNION ,  Mark RANDOLPH ,  Meng DING

Inventor： Ashot MELIK-MARTIROSIAN ,  Ed RUNNION ,  Mark RANDOLPH ,  Meng DING

IPC: G11C16/06 ,  G11C7/00 ,  G11C16/04

CPC classification number: G11C16/0475 ,  G11C16/12 ,  G11C16/344 ,  G11C16/3445 ,  G11C16/3454 ,  G11C16/3459

Abstract: A flash memory system configured in accordance with an example embodiment of the invention employs a virtual ground array architecture. During programming operations, target memory cells are biased with a positive source bias voltage to reduce or eliminate leakage current that might otherwise conduct through the target memory cells. A positive source bias voltage may also be applied to target memory cells during verification operations (program verify, soft program verify, erase verify) to reduce or eliminate leakage current that might otherwise introduce errors in the verification operations.

Abstract translation: 根据本发明的示例性实施例配置的闪存系统采用虚拟接地阵列架构。 在编程操作期间，目标存储器单元被偏置为正的源偏置电压，以减少或消除否则可能通过目标存储器单元传导的漏电流。 在验证操作（程序验证，软程序验证，擦除验证）期间，也可以将正源偏置电压施加到目标存储器单元，以减少或消除可能在验证操作中引入错误的泄漏电流。

公开(公告)号：US07630253B2

公开(公告)日：2009-12-08

申请号：US11398415

申请日：2006-04-05

Applicant: Ashot Melik-Martirosian ,  Ed Runnion ,  Mark Randolph ,  Meng Ding

Inventor： Ashot Melik-Martirosian ,  Ed Runnion ,  Mark Randolph ,  Meng Ding

IPC: G11C16/04

CPC classification number: G11C16/0475 ,  G11C16/12 ,  G11C16/344 ,  G11C16/3445 ,  G11C16/3454 ,  G11C16/3459

Abstract: A flash memory system configured in accordance with an example embodiment of the invention employs a virtual ground array architecture. During programming operations, target memory cells are biased with a positive source bias voltage to reduce or eliminate leakage current that might otherwise conduct through the target memory cells. A positive source bias voltage may also be applied to target memory cells during verification operations (program verify, soft program verify, erase verify) to reduce or eliminate leakage current that might otherwise introduce errors in the verification operations.

Abstract translation: 根据本发明的示例性实施例配置的闪存系统采用虚拟接地阵列架构。 在编程操作期间，目标存储器单元被偏置为正的源偏置电压，以减少或消除否则可能通过目标存储器单元传导的漏电流。 在验证操作（程序验证，软程序验证，擦除验证）期间，也可以将正源偏置电压施加到目标存储器单元，以减少或消除可能在验证操作中引入错误的泄漏电流。

公开(公告)号：US07564091B2

公开(公告)日：2009-07-21

申请号：US12199692

申请日：2008-08-27

Applicant: Chungho Lee ,  Ashot Melik-Martirosian ,  Hiroyuki Kinoshita ,  Kuo-Tung Chang ,  Amol Joshi ,  Meng Ding

Inventor： Chungho Lee ,  Ashot Melik-Martirosian ,  Hiroyuki Kinoshita ,  Kuo-Tung Chang ,  Amol Joshi ,  Meng Ding

IPC: H01L29/76 ,  H01L29/788

CPC classification number: H01L21/28282 ,  H01L29/42332 ,  H01L29/66833 ,  H01L29/7887 ,  H01L29/7923

Abstract: A semiconductor memory device and a method for its fabrication are provided. In accordance with one embodiment of the invention the method comprises the steps of forming a gate insulator and a gate electrode overlying a semiconductor substrate. The gate insulator is etched to form an undercut opening beneath an edge of the gate electrode and the undercut opening is filled with a layered structure comprising a charge trapping layer sandwiched between layers of oxide and nitride. A region of the semiconductor substrate is impurity doped to form a bit line aligned with the gate electrode, and a conductive layer is deposited and patterned to form a word line coupled to the gate electrode.

Abstract translation: 提供半导体存储器件及其制造方法。 根据本发明的一个实施例，该方法包括以下步骤：形成栅极绝缘体和覆盖半导体衬底的栅电极。 蚀刻栅极绝缘体以在栅电极的边缘下方形成底切开口，并且底切开口填充有包括夹在氧化物层和氮化物层之间的电荷捕获层的分层结构。 掺杂半导体衬底的区域以形成与栅电极对准的位线，并且沉积并图案化导电层以形成耦合到栅电极的字线。

公开(公告)号：US07538383B1

公开(公告)日：2009-05-26

申请号：US11416703

申请日：2006-05-03

Applicant: Meng Ding ,  Simon S. Chan

Inventor： Meng Ding ,  Simon S. Chan

IPC: H01L29/792

CPC classification number: H01L29/7923 ,  H01L27/115 ,  H01L27/11568

Abstract: According to one exemplary embodiment, a two-bit memory cell includes a gate stack situated over a substrate, where the gate stack includes a charge-trapping layer. The charge-trapping layer includes first and second conductive segments and a nitride segment, where the nitride segment is situated between the first and second conductive segments. The nitride segment electrically insulates the first conductive segment from the second conductive segment. The first and second conductive segments provide respective first and second data bit storage locations in the two-bit memory cell. The gate stack can further include a lower oxide segment situated between the substrate and the charge-trapping layer. The gate stack can further include an upper oxide segment situated over the charge-trapping layer. The gate stack can be situated between a first dielectric segment and a second dielectric segment, where the first and second dielectric segments are situated over respective first and second bitlines.

Abstract translation: 根据一个示例性实施例，两比特存储器单元包括位于衬底上方的栅极堆叠，其中栅极堆叠包括电荷捕获层。 电荷捕获层包括第一和第二导电段和氮化物区段，其中氮化物区段位于第一和第二导电区段之间。 氮化物区段将第一导电段与第二导电段电绝缘。 第一和第二导电段在双位存储单元中提供相应的第一和第二数据位存储单元。 栅极堆叠还可以包括位于衬底和电荷俘获层之间的较低氧化物段。 栅极堆叠还可以包括位于电荷捕获层上方的上部氧化物段。 栅极堆叠可以位于第一介电段和第二介电段之间，其中第一和第二介电段位于相应的第一和第二位线之上。

公开(公告)号：US07339222B1

公开(公告)日：2008-03-04

申请号：US11416551

申请日：2006-05-03

Applicant: Meng Ding ,  Hidehiko Shiraiwa ,  Mark Randolph

Inventor： Meng Ding ,  Hidehiko Shiraiwa ,  Mark Randolph

IPC: H01L27/108

CPC classification number: H01L27/115 ,  H01L27/11517 ,  Y10S257/905

Abstract: According to one exemplary embodiment, a method for fabricating a memory array includes forming a number of trenches in a substrate, where the trenches determine a number of wordline regions in the substrate, where each of the wordline regions is situated between two adjacent trenches, and where each of the wordline regions have a wordline region width. The memory array can be a flash memory array. The method further includes forming a number of bitlines in the substrate, where the bitlines are situated perpendicular to the trenches. The method further includes forming a dielectric region in each of the trenches. The method further includes forming a dielectric stack over the bitlines, wordline regions, and trenches. The method further includes forming a number of wordlines, where each wordline is situated over one of the wordline regions. The wordline region width determines an active wordline width of each of the wordlines.

Abstract translation: 根据一个示例性实施例，一种用于制造存储器阵列的方法包括在衬底中形成多个沟槽，其中沟槽确定衬底中的多个字线区域，其中每个字线区域位于两个相邻的沟槽之间，以及 其中每个字线区域具有字线区域宽度。 存储器阵列可以是闪存阵列。 该方法还包括在衬底中形成多个位线，其中位线垂直于沟槽定位。 该方法还包括在每个沟槽中形成电介质区域。 该方法还包括在位线，字线区域和沟槽之间形成电介质叠层。 该方法还包括形成多个字线，其中每个字线位于一个字线区域上。 字线区域宽度决定每个字线的有效字线宽度。

公开(公告)号：US20080032475A1

公开(公告)日：2008-02-07

申请号：US11462009

申请日：2006-08-02

Applicant: Amol Ramesh Joshi ,  Meng Ding ,  Takashi Orimoto

Inventor： Amol Ramesh Joshi ,  Meng Ding ,  Takashi Orimoto

IPC: H01L21/336

CPC classification number: H01L27/115 ,  H01L29/40117 ,  H01L29/4234 ,  H01L29/42348

Abstract: A memory cell system is provided including forming a first insulator layer over a semiconductor substrate, forming a charge trap layer having a gradient of a silicon above and below the charge trap layer over the first insulator layer, and forming a second insulator layer over the charge trap layer.

Abstract translation: 提供了一种存储单元系统，包括在半导体衬底上形成第一绝缘体层，在第一绝缘体层之上形成具有在电荷陷阱层上方和下方的硅的梯度的电荷陷阱层，并且在电荷上形成第二绝缘体层 陷阱层。

公开(公告)号：US20080032464A1

公开(公告)日：2008-02-07

申请号：US11461998

申请日：2006-08-02

Applicant: Amol Ramesh Joshi ,  Meng Ding ,  Takashi Orimoto

Inventor： Amol Ramesh Joshi ,  Meng Ding ,  Takashi Orimoto

IPC: H01L21/8232 ,  H01L21/335

CPC classification number: H01L27/115 ,  H01L27/11568

Abstract: A memory cell system is provided including forming a first insulator layer over a semiconductor substrate, forming a first intermediate layer over the first insulator layer, forming a charge trap layer over the first intermediate layer, forming a second intermediate layer over the charge trap layer, and forming a second insulator layer with the second intermediate layer.

Abstract translation: 提供一种存储单元系统，包括在半导体衬底上形成第一绝缘体层，在第一绝缘体层上形成第一中间层，在第一中间层上形成电荷陷阱层，在电荷陷阱层上形成第二中间层， 以及与所述第二中间层形成第二绝缘体层。

公开(公告)号：US07291279B2

公开(公告)日：2007-11-06

申请号：US10835807

申请日：2004-04-30

Applicant: Frederick Hayes Dill ,  Meng Ding ,  Kuok San Ho ,  Jordan Asher Katine ,  Scott Arthur MacDonald ,  Huey-Ming Tzeng

Inventor： Frederick Hayes Dill ,  Meng Ding ,  Kuok San Ho ,  Jordan Asher Katine ,  Scott Arthur MacDonald ,  Huey-Ming Tzeng

IPC: B44C1/22 ,  H01L21/00 ,  G11B5/33 ,  G11B5/127

CPC classification number: G11B5/3906 ,  G11B5/3163 ,  G11B5/40 ,  Y10T29/49021 ,  Y10T29/49043 ,  Y10T29/49048

Abstract: A method of making a read sensor while protecting it from electrostatic discharge (ESD) damage involves forming a severable shunt during the formation of the read sensor. The method may include forming a resist layer over a plurality of read sensor layers; performing lithography with use of a mask to form the resist layer into a patterned resist which exposes left and right side regions over the read sensor layers as well as a shunt region; etching, with the patterned resist in place, to remove materials in the left and right side regions and in the shunt region; and depositing, with the patterned resist in place, left and right hard bias and lead layers in the left and right side regions, respectively, and in the shunt region for forming a severable shunt which electrically couples the left and right hard bias and lead layers together for ESD protection.

Abstract translation: 制造读取传感器同时防止静电放电（ESD）损坏的方法包括在形成读取的传感器期间形成可分离的分流。 该方法可以包括在多个读取传感器层上形成抗蚀剂层; 使用掩模执行光刻以将抗蚀剂层形成图案化的抗蚀剂，其在读取的传感器层以及分流区域上暴露左侧区域和右侧区域; 蚀刻，图案化抗蚀剂就位，以去除左右侧区域和分流区域中的材料; 并且分别在左侧区域和右侧区域以及分流区域中分别将图案化的抗蚀剂沉积在左侧和右侧的硬偏压和引线层，以形成可分离的分流器，其将左右硬偏压和引线层电耦合 一起为ESD保护。