公开(公告)号：US08441085B2

公开(公告)日：2013-05-14

申请号：US12849675

申请日：2010-08-03

申请人： Koichi Nagasawa ,  Takashi Yamaguchi ,  Nobutaka Ozaki ,  Yasuhiro Kanaya ,  Hirohisa Takeda ,  Yasuo Mikami ,  Yoshifumi Mutoh

发明人： Koichi Nagasawa ,  Takashi Yamaguchi ,  Nobutaka Ozaki ,  Yasuhiro Kanaya ,  Hirohisa Takeda ,  Yasuo Mikami ,  Yoshifumi Mutoh

IPC分类号： H01L27/14 ,  H01L31/00

CPC分类号： H01L29/78633 ,  G02F1/133555 ,  G02F1/13394 ,  G02F1/136227 ,  H01L27/1248

摘要： An electronic apparatus having a substrate with a bottom gate p-channel type thin film transistor; a resist pattern over the substrate; and a light shielding film operative to block light having a wavelength shorter than 260 nm over at least a channel part of said thin film transistor.

摘要翻译： 一种具有底栅p沟道型薄膜晶体管的衬底的电子设备; 衬底上的抗蚀剂图案; 以及遮光膜，其操作来阻挡在所述薄膜晶体管的至少通道部分上具有短于260nm的波长的光。

公开(公告)号：US20120305920A1

公开(公告)日：2012-12-06

申请号：US13469344

申请日：2012-05-11

申请人： Koichi Nagasawa ,  Masanobu Ikeda ,  Yasuhiro Murata

发明人： Koichi Nagasawa ,  Masanobu Ikeda ,  Yasuhiro Murata

IPC分类号： H01L29/786 ,  H01L21/768 ,  H01L27/15

CPC分类号： H01L23/5226 ,  H01L21/76804 ,  H01L27/1244 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device including: a first electric conductor of a lower layer side and a second electric conductor of an upper layer side; a thick film insulating layer provided between the first electric conductor and the second electric conductor; and a contact portion formed so as to imitate an inner surface shape of a through hole with respect to the insulating layer and electrically connecting the first electric conductor and the second electric conductor, in which a tapered angle of the through hole is an acute angle.

摘要翻译： 一种半导体器件，包括：下层侧的第一导电体和上层侧的第二导电体; 设置在所述第一电导体和所述第二电导体之间的厚膜绝缘层; 以及形成为相对于所述绝缘层模拟贯通孔的内表面形状并电连接所述第一导电体和所述第二导电体的接触部，所述第一导电体和所述第二导电体的通孔的锥角为锐角。

公开(公告)号：US07678684B2

公开(公告)日：2010-03-16

申请号：US11878666

申请日：2007-07-26

申请人： Yasushi Koubuchi ,  Koichi Nagasawa ,  Masahiro Moniwa ,  Youhei Yamada ,  Toshifumi Takeda

发明人： Yasushi Koubuchi ,  Koichi Nagasawa ,  Masahiro Moniwa ,  Youhei Yamada ,  Toshifumi Takeda

IPC分类号： H01L21/302

CPC分类号： H01L23/562 ,  G03F9/7076 ,  G03F9/7084 ,  H01L21/31053 ,  H01L21/76819 ,  H01L21/76838 ,  H01L23/522 ,  H01L23/585 ,  H01L24/05 ,  H01L24/10 ,  H01L24/13 ,  H01L2224/0401 ,  H01L2224/05554 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01058 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01082 ,  H01L2924/05042 ,  H01L2924/12042 ,  H01L2924/1305 ,  H01L2924/1306 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/30105 ,  H01L2924/00

摘要： Interconnections are formed over an interlayer insulating film which covers MISFETQ1 formed on the principal surface of a semiconductor substrate, while dummy interconnections are disposed in a region spaced from such interconnections. Dummy interconnections are disposed also in a scribing area. Dummy interconnections are not formed at the peripheries of a bonding pad and a marker. In addition, a gate electrode of a MISFET and a dummy gate interconnection formed of the same layer are disposed. Furthermore, dummy regions are disposed in a shallow trench element-isolation region. After such dummy members are disposed, an insulating film is planarized by the CMP method.

摘要翻译： 在覆盖形成在半导体衬底的主表面上的MISFETQ1的层间绝缘膜上形成互连，而虚设互连设置在与这种相互连接的区域中。 虚拟互连也布置在划线区域中。 在接合焊盘和标记的周边不形成虚拟互连。 此外，设置MISFET的栅电极和由相同层形成的虚拟栅极互连。 此外，虚设区域设置在浅沟槽元件隔离区域中。 在这样的虚设部件设置之后，通过CMP方法将绝缘膜平坦化。

公开(公告)号：US20100033668A1

公开(公告)日：2010-02-11

申请号：US12510402

申请日：2009-07-28

申请人： Takeo Koito ,  Koichi Nagasawa ,  Shuji Hayashi ,  Hidehiro Kosaka

发明人： Takeo Koito ,  Koichi Nagasawa ,  Shuji Hayashi ,  Hidehiro Kosaka

IPC分类号： G02F1/1339 ,  G02F1/13

CPC分类号： G02F1/13338 ,  G02F1/13394 ,  G02F2001/13396

摘要： A liquid-crystal display device includes a first substrate; a second substrate formed so as to oppose the first substrate; a liquid-crystal layer with a predetermined thickness, the liquid-crystal layer being formed between the first substrate and the second substrate; a planarization film for planarizing the surface of the liquid-crystal layer, the planarization film being formed on the surface of at least one of the first substrate and the second substrate, the surface facing the liquid-crystal layer; and projecting parts that are integrally formed with the planarization film.

摘要翻译： 液晶显示装置包括：第一基板; 形成为与第一基板相对的第二基板; 具有预定厚度的液晶层，所述液晶层形成在所述第一基板和所述第二基板之间; 平坦化膜，用于使液晶层的表面平坦化，所述平坦化膜形成在所述第一基板和所述第二基板中的至少一个的表面上，所述表面面向所述液晶层; 以及与平坦化膜一体形成的突出部。

公开(公告)号：US20090134461A1

公开(公告)日：2009-05-28

申请号：US12275448

申请日：2008-11-21

申请人： Koichi Nagasawa ,  Takashi Yamaguchi ,  Nobutaka Ozaki ,  Yasuhiro Kanaya ,  Hirohisa Takeda ,  Yasuo Mikami ,  Yoshifumi Mutoh

发明人： Koichi Nagasawa ,  Takashi Yamaguchi ,  Nobutaka Ozaki ,  Yasuhiro Kanaya ,  Hirohisa Takeda ,  Yasuo Mikami ,  Yoshifumi Mutoh

IPC分类号： H01L27/12 ,  H01L21/84

CPC分类号： H01L29/78633 ,  G02F1/133555 ,  G02F1/13394 ,  G02F1/136227 ,  H01L27/1248

摘要： A method of manufacturing an electronic apparatus having a resist pattern provided over a substrate provided with a thin film transistor, the method includes the steps of forming by application a resist film over the substrate in the state of covering the thin film transistor, forming a resist pattern by subjecting the resist film to exposure to light and a developing treatment, and irradiating the resist pattern with at least one of ultraviolet light and visible light in a dry atmosphere in the condition where a channel part of the thin film transistor is prevented from being irradiated with light having a wavelength of shorter than 260 nm, wherein a step of heat curing the resist pattern is conducted after the irradiation with at least one of ultraviolet light and visible light.

摘要翻译： 一种制造具有设置在设置有薄膜晶体管的基板上的抗蚀剂图案的电子设备的方法，该方法包括以下步骤：在覆盖薄膜晶体管的状态下在基板上施加抗蚀剂膜，形成抗蚀剂 通过使抗蚀剂膜曝光并进行显影处理，并且在防止薄膜晶体管的沟道部分被阻止的条件下，在干燥气氛中用紫外光和可见光中的至少一种照射抗蚀剂图案 用波长短于260nm的光照射，其中在用紫外光和可见光中的至少一种照射之后进行热固化抗蚀图案的步骤。

公开(公告)号：US20070222001A1

公开(公告)日：2007-09-27

申请号：US11802450

申请日：2007-05-23

申请人： Yasushi Koubuchi ,  Koichi Nagasawa ,  Masahiro Moniwa ,  Youhei Yamada ,  Toshifumi Takeda

发明人： Yasushi Koubuchi ,  Koichi Nagasawa ,  Masahiro Moniwa ,  Youhei Yamada ,  Toshifumi Takeda

IPC分类号： H01L29/94 ,  H01L23/48

CPC分类号： H01L23/562 ,  G03F9/7076 ,  G03F9/7084 ,  H01L21/31053 ,  H01L21/76819 ,  H01L21/76838 ,  H01L23/522 ,  H01L23/585 ,  H01L24/05 ,  H01L24/10 ,  H01L24/13 ,  H01L2224/0401 ,  H01L2224/05554 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01058 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01082 ,  H01L2924/05042 ,  H01L2924/12042 ,  H01L2924/1305 ,  H01L2924/1306 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/30105 ,  H01L2924/00

摘要： Interconnections are formed over an interlayer insulating film which covers MISFETQ1 formed on the principal surface of a semiconductor substrate, while dummy interconnections are disposed in a region spaced from such interconnections. Dummy interconnections are disposed also in a scribing area. Dummy interconnections are not formed at the peripheries of a bonding pad and a marker. In addition, a gate electrode of a MISFET and a dummy gate interconnection formed of the same layer are disposed. Furthermore, dummy regions are disposed in a shallow trench element-isolation region. After such dummy members are disposed, an insulating film is planarized by the CMP method.

公开(公告)号：US07274074B2

公开(公告)日：2007-09-25

申请号：US10619039

申请日：2003-07-14

申请人： Yasushi Koubuchi ,  Koichi Nagasawa ,  Masahiro Moniwa ,  Youhei Yamada ,  Toshifumi Takeda

发明人： Yasushi Koubuchi ,  Koichi Nagasawa ,  Masahiro Moniwa ,  Youhei Yamada ,  Toshifumi Takeda

IPC分类号： H01L29/76

CPC分类号： H01L23/562 ,  G03F9/7076 ,  G03F9/7084 ,  H01L21/31053 ,  H01L21/76819 ,  H01L21/76838 ,  H01L23/522 ,  H01L23/585 ,  H01L24/05 ,  H01L24/10 ,  H01L24/13 ,  H01L2224/0401 ,  H01L2224/05554 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01058 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01082 ,  H01L2924/05042 ,  H01L2924/12042 ,  H01L2924/1305 ,  H01L2924/1306 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/30105 ,  H01L2924/00

摘要： Interconnections are formed over an interlayer insulating film which covers MISFETQ1 formed on the principal surface of a semiconductor substrate, while dummy interconnections are disposed in a region spaced from such interconnections. Dummy interconnections are disposed also in a scribing area. Dummy interconnections are not formed at the peripheries of a bonding pad and a marker. In addition, a gate electrode of a MISFET and a dummy gate interconnection formed of the same layer are disposed. Furthermore, dummy regions are disposed in a shallow trench element-isolation region. After such dummy members are disposed, an insulating film is planarized by the CMP method.

公开(公告)号：US07250682B2

公开(公告)日：2007-07-31

申请号：US10956159

申请日：2004-10-04

申请人： Yasushi Koubuchi ,  Koichi Nagasawa ,  Masahiro Moniwa ,  Youhei Yamada ,  Toshifumi Takeda

发明人： Yasushi Koubuchi ,  Koichi Nagasawa ,  Masahiro Moniwa ,  Youhei Yamada ,  Toshifumi Takeda

IPC分类号： H01L23/52

CPC分类号： H01L23/562 ,  G03F9/7076 ,  G03F9/7084 ,  H01L21/31053 ,  H01L21/76819 ,  H01L21/76838 ,  H01L23/522 ,  H01L23/585 ,  H01L24/05 ,  H01L24/10 ,  H01L24/13 ,  H01L2224/0401 ,  H01L2224/05554 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01058 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01082 ,  H01L2924/05042 ,  H01L2924/12042 ,  H01L2924/1305 ,  H01L2924/1306 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/30105 ,  H01L2924/00

摘要： Interconnections are formed over an interlayer insulating film which covers MISFETQ1 formed on the principal surface of a semiconductor substrate, while dummy interconnections are disposed in a region spaced from such interconnections. Dummy interconnections are disposed also in a scribing area. Dummy interconnections are not formed at the peripheries of a bonding pad and a marker. In addition, a gate electrode of a MISFET and a dummy gate interconnection formed of the same layer are disposed. Furthermore, dummy regions are disposed in a shallow trench element-isolation region. After such dummy members are disposed, an insulating film is planarized by the CMP method.

摘要翻译： 在覆盖形成在半导体衬底的主表面上的MISFETQ 1的层间绝缘膜上形成互连，而虚设互连设置在与这种相互连接的区域中。 虚拟互连也布置在划线区域中。 在接合焊盘和标记的周边不形成虚拟互连。 此外，设置MISFET的栅电极和由相同层形成的虚拟栅极互连。 此外，虚设区域设置在浅沟槽元件隔离区域中。 在这样的虚设部件设置之后，通过CMP方法将绝缘膜平坦化。

公开(公告)号：US20050026405A1

公开(公告)日：2005-02-03

申请号：US10926142

申请日：2004-08-26

申请人： Yasushi Koubuchi ,  Koichi Nagasawa ,  Masahiro Moniwa ,  Youhei Yamada ,  Toshifumi Takeda

发明人： Yasushi Koubuchi ,  Koichi Nagasawa ,  Masahiro Moniwa ,  Youhei Yamada ,  Toshifumi Takeda

IPC分类号： H01L21/76 ,  H01L21/304 ,  H01L21/3205 ,  H01L21/768 ,  H01L21/8242 ,  H01L23/00 ,  H01L27/108 ,  H01L21/336

CPC分类号： H01L23/562 ,  G03F9/7076 ,  G03F9/7084 ,  H01L21/31053 ,  H01L21/76819 ,  H01L21/76838 ,  H01L23/522 ,  H01L23/585 ,  H01L24/05 ,  H01L24/10 ,  H01L24/13 ,  H01L2224/0401 ,  H01L2224/05554 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01058 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01082 ,  H01L2924/05042 ,  H01L2924/12042 ,  H01L2924/1305 ,  H01L2924/1306 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/30105 ,  H01L2924/00

摘要： Interconnections are formed over an interlayer insulating film which covers MISFETQ1 formed on the principal surface of a semiconductor substrate, while dummy interconnections are disposed in a region spaced from such interconnections. Dummy interconnections are disposed also in a scribing area. Dummy interconnections are not formed at the peripheries of a bonding pad and a marker. In addition, a gate electrode of a MISFET and a dummy gate interconnection formed of the same layer are disposed. Furthermore, dummy regions are disposed in a shallow trench element-isolation region. After such dummy members are disposed, an insulating film is planarized by the CMP method.

摘要翻译： 在覆盖形成在半导体衬底的主表面上的MISFETQ1的层间绝缘膜上形成互连，而虚设互连设置在与这种相互连接的区域中。 虚拟互连也布置在划线区域中。 在接合焊盘和标记的周边不形成虚拟互连。 此外，设置MISFET的栅电极和由相同层形成的虚拟栅极互连。 此外，虚设区域设置在浅沟槽元件隔离区域中。 在这样的虚设部件设置之后，通过CMP方法将绝缘膜平坦化。

公开(公告)号：US06423139B1

公开(公告)日：2002-07-23

申请号：US09153590

申请日：1998-09-15

申请人： Futoshi Shimai ,  Koichi Nagasawa ,  Junji Kutsuzawa

发明人： Futoshi Shimai ,  Koichi Nagasawa ,  Junji Kutsuzawa

IPC分类号： B05C502

CPC分类号： H01L21/6715 ,  B05C5/0254 ,  B05C11/08 ,  H01L21/67051

摘要： A liquid chemical treatment apparatus includes a coating apparatus for applying a coating liquid such as resist onto the surface of a substantially planar substrate such as a glass substrate. The coating apparatus includes a nozzle with an elongate injection outlet such as a slit with a width substantially the same as that of the substrate, and a liquid circulating passage connected to the nozzle for supplying the coating liquid to the nozzle. Mechanisms are provided with the circulating passage and the nozzle to remove air from the liquid, and to maintain the circulating liquid at a substantially constant temperature and a substantially constant flow rate. When performing a coating operation with the coating liquid, a flow amount thereof is increased up to 1,500 though 3,000 ml/min, from a condition under which the liquid is prevented from dropping from the slit-like injection outlet while circulating within the circulating passage at a flow rate of 500 through 700 ml/min, for example, by closing a valve or by means of a pump 35 included with the passage. The liquid output from the slit-like injection outlet 4a takes on the form of a curtain to be applied over substantially the entire surface of the substrate, without any drops of the coating liquid remaining within the nozzle after the coating operation.

摘要翻译： 液体化学处理装置包括用于将诸如抗蚀剂的涂布液施加到诸如玻璃基板的基本平坦的基板的表面上的涂覆装置。 涂布装置包括具有细长的注射口的喷嘴，例如宽度与基底宽度基本相同的狭缝，以及连接到喷嘴的液体循环通道，用于向喷嘴供应涂布液。 提供了循环通道和喷嘴以从液体中除去空气并且将循环液体保持在基本上恒定的温度和基本上恒定的流速的机构。 当用涂布液进行涂布操作时，其流量可以从循环通道中循环的液体被防止从狭缝状喷射出口滴落的状态增加到1500〜3000ml / min 流量为500至700ml / min，例如通过关闭阀或通过通道附带的泵35。 从狭缝状喷射出口输出的液体呈窗帘的形式施加在基体的基本整个表面上，涂布操作之后没有任何滴落的喷涂液体残留在喷嘴内。