Invention Publication
- Patent Title: 3D SEMICONDUCTOR DEVICE AND STRUCTURE WITH BONDING AND DRAM MEMORY CELLS
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Application No.: US18424790Application Date: 2024-01-27
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Publication No.: US20240213073A1Publication Date: 2024-06-27
- Inventor: Zvi Or-Bach , Brian Cronquist , Deepak C. Sekar
- Applicant: Monolithic 3D Inc.
- Applicant Address: US OR Klamath Falls
- Assignee: Monolithic 3D Inc.
- Current Assignee: Monolithic 3D Inc.
- Current Assignee Address: US OR Klamath Falls
- Main IPC: H01L21/683
- IPC: H01L21/683 ; G11C8/16 ; H01L21/74 ; H01L21/762 ; H01L21/768 ; H01L21/822 ; H01L21/8238 ; H01L21/84 ; H01L23/00 ; H01L23/367 ; H01L23/48 ; H01L23/525 ; H01L25/00 ; H01L25/065 ; H01L27/02 ; H01L27/06 ; H01L27/092 ; H01L27/10 ; H01L27/105 ; H01L27/118 ; H01L27/12 ; H01L29/423 ; H01L29/66 ; H01L29/78 ; H01L29/788 ; H01L29/792 ; H10B10/00 ; H10B12/00 ; H10B20/00 ; H10B20/20 ; H10B41/20 ; H10B41/40 ; H10B41/41 ; H10B43/20 ; H10B43/40

Abstract:
A 3D semiconductor device, the device including: a first level including a first single crystal layer, the first level including first transistors, where each of the first transistors includes a single crystal channel; first metal layer; a second metal layer overlaying the first metal layer; and a second level including a second single crystal layer, the second level including second transistors and at least one third metal layer, where the second level overlays the first level, where at least one of the second transistors includes a transistor channel, where the second level includes a plurality of DRAM memory cells, where each of the plurality of DRAM memory cells includes at least one of the second transistors and one capacitor, where the second level is directly bonded to the first level, and where the bonded includes metal to metal bonds.
Public/Granted literature
- US12068187B2 3D semiconductor device and structure with bonding and DRAM memory cells Public/Granted day:2024-08-20
Information query
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