Structures and methods for testing three-dimensional (3D) memory devices (100) are disclosed. A 3D memory device (100) includes a memory array structure (102), a peripheral device structure (104), andan interconnect layer (106) in contact with a front side of the memory array structure (102) and a front side of the peripheral device structure (104), and a conductive pad (108) at a back side of the memory array structure (102) and that overlaps the memory array structure (102). The memory array structure (102) includes a memory array stack (109), a through array contact (TAC) (110) extending vertically through at least part of the memory array stack (109), and a memory array contact (112). The peripheral device structure (104) includes a test circuit (126). The interconnect layer (106) includes an interconnect structure (116, 124). The conductive pad (108), the TAC (110), the interconnect structure (116, 124), and at least one of the test circuit (126) and the memory array contact (112) are electrically connected.