US09369070B2
A method for correcting torque including: presetting rotational speed of each gear by corresponding gear input lines of a microprocessor; providing a mechanism to select one rotational speed set; electing N power points within a range of the rated power, acquiring a set of torque data corresponding to each set of the rotational speed at each power point, and storing a total 2×N sets of torque data; allowing the motor to enter the torque correction mode; recording a steady torque Tadj when the motor operates in a steady state; and comparing the steady torque Tadj with a maximum gear torque Tmax, and selecting the set of torque data to which T[M]max belongs when the steady torque Tadj satisfies the relationship: 110%×T[M−1]max
US09369067B2
A vibrational wave driving apparatus in the present invention includes an elastic member attached to an electromechanical energy transducing member, a pair of electrodes provided on the electromechanical energy transducing member, a wiring unit connecting the pair of electrodes and a voltage applying unit, and a driven body configured to be pressure contacted with the elastic member. The driven body is relatively driven by mechanical vibration of the elastic member generated when an alternating voltage is applied to the pair of electrodes. The wiring unit includes a pair of wiring portions connected to the pair of electrodes, respectively. The pair of wiring portions includes a pair of film-like bases and a pair of conductors formed on surfaces of the pair of film-like bases. The pair of wiring portions is arranged such that the pair of conductors overlaps each other through insulating layers.
US09369064B2
A current source inverter includes a controller, an input unit, a buffer unit, a modulating unit, and a commutator. The controller generates a switch control signal, an inverse switch control signal, a first pulse width modulation control signal, and a second pulse width modulation control signal. The input unit stores and transmits input power of a direct current power supply according to the first pulse width modulation control signal. The buffer unit is coupled to the input unit for receiving and transmitting the input power. The modulating unit generates and outputs a full-wave rectified sinusoidal current according to the second pulse width modulation control signal and the input power. The commutator converts the full-wave rectified sinusoidal current into an alternating current according to the switch control signal and the inverse switch control signal and outputs the alternating current to a load or a utility line.
US09369060B2
A power generation system includes an input to receive a low-voltage alternating current and a number N of voltage-conversion modules coupled to the input, each electrically connected in series. Each voltage-conversion module includes a transformer configured to convert the low-voltage alternating current into a high-voltage alternating current. Each voltage-conversion module includes a multiplier configured to convert the high-voltage alternating current from the transformer into a high-voltage direct current. The multiplier includes a positive multiplier part and a negative multiplier part. The positive multiplier part and the negative multiplier part each includes a pair of input terminals connected in parallel with the transform and at least one multiplier stage comprising a single diode and a capacitor assembly. The number N is an even number between 4 and 24.
US09369052B1
The present invention provides a plural commutated-element direct-current current transformer (DCCT) that offers wide bandwidth together with freedom from transient disturbances caused by commutation. Plural commutated elements, each comprising a commutating switch and a current transformer each generate, responsive to a commutating signal, a current in a burden, each burden generating in turn a signal representing a DCCT input current. The commutating signal for each element is out of phase with such signals driving other commutated elements. Because of this phase difference, at any given time at least one commutated element is producing a signal free of transient disturbances from commutation. A selector switch, responsive to a selector signal out of phase with all commutating signals, connects to a DCCT output terminal only a burden signal representing the input current that is presently free of transient disturbances.
US09369044B2
According to one embodiment, a power circuit includes an input terminal 1 to which a DC input voltage is applied, an output terminal 2, a first DC/DC converter which receives the DC input voltage and supplies a first phase output current to the output terminal 2, a second DC/DC converter which supplies an output current lower than the first phase output current to the output terminal in a second phase which is different from the first phase, and a controller which controls operations of the first and second DC/DC converters.
US09369043B2
A DC-DC converter includes a first differential voltage sensor to detect a first inductor current by sensing a first differential voltage across a first power stage of the DC-DC converter. A second differential voltage sensor detects a second inductor current by sensing a second differential voltage across a second power stage of the DC-DC converter. An integrator stage combines the first differential voltage from the first power stage and the second differential voltage from the second power stage to generate a compensation signal to adjust current balancing for the DC-DC converter.
US09369039B2
A driving device includes: a power source circuit that converts inputted power to a constant voltage or constant current power, and outputs this converted power; a driver circuit that supplies the power outputted by the power source circuit to a load; and a control unit that receives the voltage or current of the power outputted by the power source circuit, calculates a value by multiplying a control gain by a difference of the detected value and a constant target value, and outputs a feedback signal based on this calculated value to the power source circuit, thereby performing feedback control on the power source circuit, the control unit raising the control gain when the voltage or current of the power outputted by the driver circuit is changed.
US09369028B2
An electronically commutated motor, including: a motor body and a motor controller. The motor controller includes a control box and a circuit board disposed in the control box. The circuit board includes a microprocessor, an inverter circuit, a gear detection circuit, and a power supply. The gear detection circuit includes a plurality of current sensing units. The output end of the power supply supplies power to each circuit, and a first AC input end of the power supply is connected to a first power input line N. The gear detection circuit is connected to a plurality of gear input lines. At least one of the gear input lines is selected to be in an energized state. Each gear input line is correspondingly connected to a first input end of one of the current sensing units.
US09369009B2
A casing of a power transmitting device is provided with a power transmitting device side passive electrode, a power transmitting device side active electrode, and a power transmitting module. A jacket mounted on a terminal is provided with a power receiving device side passive electrode, a power receiving device side active electrode, a power receiving module, and a DC-DC converter. A heat sink portion with fins is formed on a portion of the power transmitting device side passive electrode. When the terminal is mounted on the power transmitting device, the power receiving device side passive electrode is electrically connected to the power transmitting device side passive electrode, and the power receiving device side active electrode faces the power transmitting device side active electrode. In this state, the heat of the power receiving module and the DC-DC converter is dissipated from the power transmitting device side passive electrode.
US09369005B2
This disclosure describes techniques and systems for extracting energy from the endocochlear potential (EP) in animal subjects (e.g., human subjects) and using the extracted energy to operate circuits (e.g., electronic device, sensors, and transmitters). The subject matter of this disclosure is embodied, for example, in a system for extracting energy from an endocochlear potential of an animal, wherein the system includes a pair of electrodes, and a circuit coupled to the pair of electrodes. The circuit includes a boost converter, an energy buffer component configured to receive voltage from the boost converter, a start-up rectifier configured to provide voltage to the energy buffer component, and a control component configured to provide control signals to the boost converter. The power extracted from the endocochlear potential is equal or larger than the quiescent power of the circuit.
US09368997B2
Systems involving magnetic attachment for portable electronic devices and related methods are provided. In this regard, a representative system includes: a magnetic attachment system operative to generate a magnetic field, the magnetic attachment system being operative to vary a strength of the magnetic field based, at least in part, on a control input such that a portable electronic device is magnetically attached to the electronic apparatus.
US09368995B2
In a charging method for a lithium ion battery, constant current charging of the lithium ion battery is performed. The constant current charging includes at least three consecutive charging stages. The at least three consecutive charging stages include consecutive first, second, and third charging stages. The second charging stage has a set current value which is set lower than set current values of the first and third charging stages.
US09368974B2
A method or apparatus for wireless transferring energy between a source coil and a drain coil, comprises selling an initial resonant frequency of the source coil as a first condition; setting the source coil and said drain coil in positions relative to each other to define an initial coupling coefficient therebetween, so that the initial coupling coefficient comprises a second condition; and adiabatically changing one or both of the conditions while pumping energy into the source coil. The source coil energy is transferred to the drain coil over the course of the adiabatic change.
US09368971B2
A method of configuring a renewable energy curtailment and control system uses a master controller and a plurality of controllers configured to control a cluster of renewable energy resources to deliver predetermined amounts of actual power and reactive power to a point of interconnect with a grid in accordance with contractual requirements with users of electrical power while reducing reactive power flow between renewable resources in the cluster.
US09368967B1
Diodes and switching means as well as an autotransformer connect multiple AC sources of variable frequency and voltage to the utility grid, without first rectifying and thereby transferring the AC input energy to a common DC bus. Instead, the individual positive and negative AC input half waves or parts of those half waves, if and when they occur during a particular time interval, are injected into the positive or negative half wave of the utility AC power directly and respectively. The amount of energy transferred may be controlled by a microprocessor. Assuming the prime mover that generates AC voltages in multiple coils is a windmill, then the required circuitry to accomplish this energy transfer will be physically small enough to allow that circuitry to reside in the windmill itself, and thereby this energy conversion method significantly simplifies the installation of a windmill that uses this energy conversion method.
US09368964B2
A distributed power system including multiple (DC) batteries each DC battery with positive and negative poles. Multiple power converters are coupled respectively to the DC batteries. Each power converter includes a first terminal, a second terminal, a third terminal and a fourth terminal. The first terminal is adapted for coupling to the positive pole. The second terminal is adapted for coupling to the negative pole. The power converter includes: (i) a control loop adapted for setting the voltage between or current through the first and second terminals, and (ii) a power conversion portion adapted to selectively either: convert power from said first and second terminals to said third and fourth terminals to discharge the battery connected thereto, or to convert power from the third and fourth terminals to the first and second terminals to charge the battery connected thereto. Each of the power converters is adapted for serial connection to at least one other power converter by connecting respectively the third and fourth terminals, thereby forming a serial string. A power controller is adapted for coupling to the serial string. The power controller includes a control part adapted to maintain current through or voltage across the serial string at a predetermined value.
US09368940B2
To provide a semiconductor laser that suppresses end face destruction due to catastrophic optical damage (COD) to a light emission end face and has high output characteristics.An n-type clad layer, a current block layer, an active layer, and a p-type clad layer are provided over an n-type substrate whose major plane has an off-angle in a <1-100> direction from a (0001) plane. For example, the current block layer is arranged on both sides of a current constriction area. Then, the current block layer is arranged so as to be retracted from a cleavage plane (line). In this case, in the active layer having a quantum well structure that is crystal-grown over the n-type clad layer and the current block layer, the layer thickness of a window area from the cleavage plane (line) up to the end part of the current block layer is smaller than the layer thickness of the current constriction area (area between the current block layers). As a result, the band gap of the active layer in the window area becomes large, and thus it is possible to suppress end face destruction due to the COD.
US09368939B2
A method for manufacturing a laser diode device includes providing a substrate having a surface region and forming epitaxial material overlying the surface region, the epitaxial material comprising an n-type cladding region, an active region comprising at least one active layer overlying the n-type cladding region, and a p-type cladding region overlying the active layer region. The epitaxial material is patterned to form a plurality of dice, each of the dice corresponding to at least one laser device, characterized by a first pitch between a pair of dice, the first pitch being less than a design width. Each of the plurality of dice are transferred to a carrier wafer such that each pair of dice is configured with a second pitch between each pair of dice, the second pitch being larger than the first pitch.
US09368927B2
A connector is mateable with a mating connector along a mating direction. The mating connector includes a plurality of mating contacts. The connector comprising a plurality of contacts which are held by a housing. Each of the contacts has a contact portion, a terminal portion and an intersecting portion. The terminal portion is positioned at a position different from a position of the contact portion in a pitch direction perpendicular to the mating direction. The intersecting portion is positioned between the contact portion and the terminal portion. The intersecting portions intersect both the mating direction and the pitch direction in a plane which is defined by the mating direction and the pitch direction. The contacts include at least a plurality of first contacts and a plurality of second contacts. The contact portions of the second contacts are positioned apart from the contact portions of the first contacts in a predetermined direction perpendicular to both the mating direction and the pitch direction. The first contacts include signal contacts which constitute at least one differential pair. The signal contacts of the differential pair have shapes same as each other.
US09368925B2
An IS-4 terminal connector assembly includes three terminal electrodes positioned over an inner tubular member such that they are radially offset from one another. Each of the terminal ring electrodes are configured such that they can withstand both tensile and cyclical bending loads with minimal compromise in their outer geometry. Additionally, each of the terminal electrodes is configured such that they have both an inner and outer geometry that facilitates adequate insulation between a select terminal electrode and an adjacent conductor. Additionally, each of the terminal ring electrodes is configured such that they facilitate an external approach to staking a cable conductor.
US09368914B2
Communications jacks include at least first through third jackwire contacts and a flexible substrate that has a first finger and a second finger. The first jackwire contact and the third jackwire contact are each mounted on the first finger and the second jackwire contact is mounted on the second finger.
US09368912B1
The jumper cables with keyed connectors includes a set of jumper cables that include keyed connectors in-line in order to prevent a short across a vehicular electrical circuit or an explosion of a vehicular battery. The jumper cables with keyed connectors include a positive line and a negative line. Both the positive line and the negative line include male plugs that are keyed to connect with receptacles built onto the vehicular batteries. The plurality of connection units insures that only the appropriate components plug together thereby preventing inadvertent shorting across the jumper cables.
US09368907B2
A male connector (20) for connection to a female connector (30) to form a water tight connector (40) is disclosed. A plug connector body (2) and a connector overmold (5) are connected together where the plug connector body (2) of hard urethane material is molded with no mold parting lines. The soft connector overmold (5) of soft urethane is fitted about a portion of the plug connector body (2) with heat applied such that the plug body (2) and overmold (5) are fused together along their connecting surfaces so that substantially no water ingress into the connection of plug body (2) and connector overmold (5) is possible. An “O” ring (14) is placed in an annular space (12) defined between facing shoulders of the connector overmold (5) and the plug connector body (2). Annular alignment keyways (16) of; the female connector (30) engage the “O” ring (14) to seal the male connector (20) and female connector (30) from water ingress.
US09368906B2
A terminal to be inserted into a storage space formed in a housing includes a hollow sheath portion, and a first engagement portion to be engaged with the storage space, the first engagement portion including a first inclining portion, and a first abutment portion extending from an upper end of the first inclining portion towards the sheath portion and making abutment at a lower end thereof with a ceiling of the sheath portion, the terminal being formed of a single metal sheet, the first engagement portion being formed by bending a projecting part around a direction intersecting with the axis of the sheath portion, the projecting part being a part of the metal sheet defining the sheath portion and extending in parallel with a direction in which the terminal is inserted into the housing.
US09368905B2
An electrical chamber is disclosed herein. The electrical chamber can include at least one wall forming a cavity, where the at least one wall includes a first end and an inner surface. The electrical chamber can also include a first isolation zone disposed on the inner surface at a first distance from the first end, where the first isolation zone is formed by a first bridge, a first underhang, and a first isolation zone inner surface, where the first bridge protrudes inward toward the cavity from the inner surface, and where the first underhang extends from a distal end of the first bridge. The cavity can be configured to receive at least one electrical conductor. The cavity and the first isolation zone can be configured to receive a potting compound.
US09368902B2
A connector according to an aspect of the invention is a connector provided with a rear connector that includes a rear housing, and a front connector that includes a front housing and that is assembled to the rear connector; the rear housing contains a terminal of a cable end, and the front housing contains a mating terminal to be connected to the terminal; and the rear housing is provided with a checking window through which the terminal is exposed to outside and a voltage of the terminal can be checked, and a waterproof lid which closes the checking window in a sealed state.
US09368898B2
A conductive connecting terminal has a main body which includes a front section, a rear section and an intermediate section between the front section and the rear section. The conductive connecting terminal also has a sealing member surrounding an outer surface of the intermediate section and forming a transition connecting surface with the outer surface of the intermediate section. The sealing member is inseparably fixed on the intermediate section. The embodiments further provide an array of conductive connecting terminals formed by stamping and having a plurality of conductive connecting terminals arranged in parallel and connected at their respective rear ends through a carrier.
US09368895B2
The terminal has a base portion held by a terminal holding member, and a contact arm portion extending from the base portion and contacting the contact portion of another terminal. In this terminal, the contact arm portion includes a cantilevered first frame portion and second frame portion extending from the base portion, a connecting frame portion connecting a free end of the first frame portion and a free end of the second frame portion, a contact protruding portion formed in the first frame portion, and a contact face formed in the contact protruding portion; and the contact face moves in a parallel direction and maintains contact with a contact face of a contact portion of another terminal when the contact arm portion is elastically deformed by contact with the contact portion of the other terminal.
US09368888B2
An electrical connector (100) includes an insulating housing (5) with a plurality of contacts received therein, a load plate (1) covering on the insulating housing (5) and a screwing member (2) assembled to the load plate (1). The screwing member (2) includes a head portion (20) with a plurality of tooth portions (201), the load plate (1) includes a tongue portion (12) with a fixing hole (120) for the screwing member (2) going through, a recess (121) near the fixing hole (120) and a block (1210) in the recess (121), during the process of screwing the screwing member (2), the tooth portions (201) touch with the block (1210) for making a sound.
US09368887B2
An apparatus including a socket forming at least one compartment together with a printed circuit board assembly. The compartment including a first side wall, a second side wall, a ceiling, and an opening for receiving one pluggable transceiver, such that when the pluggable transceiver is inserted into the opening, a transceiver contact of the pluggable transceiver is connected to a respective board contact of the printed circuit board assembly. A clamping means is arranged along at least one surface of: the first side wall, the second side wall and the ceiling, to exert a pressure on the pluggable transceiver towards a surface that is opposed the surface on which the clamping means is arranged. The opposed being one of: the second side wall, the first side wall, and the printed circuit board assembly, when the pluggable transceiver is inserted into the opening.
US09368883B2
A multi-cable connector includes a main body, a plurality of cable assemblies, and a fixing unit. The cable assemblies are inserted into the main body. Each cable assembly has a connecting head and a cable. The fixing unit is installed on the main body. The fixing unit has a plurality of notches for providing the cables to respectively couple there-through. The fixing unit abuts against the connecting heads for holding the connecting heads between the main body and the fixing unit.
US09368882B2
An electrical device having an electrical component, which has an electric terminal, and a busbar assembly having a busbar and a frame. The busbar is formed of a strip of conductive material and has first and second busbar sides that are opposite from one another. The frame has a busbar seat and a cover member. The busbar seat extends through a first frame side of the frame. The busbar is received into the busbar seat and seated to the frame such that the first busbar side is spaced apart from the first frame side so that the busbar is contained wholly within the frame. The cover member abuts the second busbar side and defines an irradiation aperture that is configured to receive a laser beam from a laser welder therethrough. A laser weld fuses the busbar to the electric terminal.
US09368877B2
A multi-array antenna having superior electrical properties is disclosed. The multi-array antenna includes a reflector plate; first radiators arranged over a surface of the reflector plate and configured to form a first beam; and second radiators arranged over a surface of the reflector plate and configured to form a second beam. Here, one of the first radiators and one of the second radiators are arranged in an imaginary first line along a lengthwise direction of the reflector plate, another one of the first radiators and another one of the second radiators are arranged in an imaginary second line, the first radiator arranged in the first line and the first radiator arranged in the second line are positioned in a diagonal direction, and the second radiator arranged in the first line and the second radiator arranged in the second line are positioned in a diagonal direction.
US09368872B2
Methods relating to providing a tuned miniature antenna and/or encapsulating such antenna inside the energy storage device.
US09368848B2
An aluminum-halogen fuel cell has a positive electrode (2), a negative electrode (3), and an electrolyte (4) containing an ionic liquid represented by formula (1) or the like. In formula (1), R1 represents an unsubstituted or substituent-containing C1 to C20 alkyl group, R2 represents a C1 to C4 alkyl group or the like, each of R3 and R4 independently represents a hydrogen atom or the like, X represents AlCl4 or the like, and Y represents Al2Cl7 or the like.
US09368841B2
A vehicle is disclosed comprising a battery and a controller. Projected battery impedance parameters are calculated based on predetermined parameter values and historical parameter values generated by a battery parameter estimation model. The values may be weighted according to time data associated with the historical impedance parameter values and a temperature of the battery. Recent historical impedance parameter values may affect the projected battery impedance parameter values more than older historical impedance parameter values. The model is initialized with projected parameter values at vehicle initialization. Battery power capability is calculated using the projected parameter values for a period of time following vehicle initialization. After the period of time following vehicle initialization, battery power capability is calculated using impedance parameters generated by the model. The period of time following vehicle initialization may end when the model output has converged to a stable solution.
US09368838B2
A battery module is configured such that n series blocks 20, each having m cells 10 connected in series, are connected in parallel. Adjacent cells 10 are connected in parallel via a first fusible link 30. One end of each of the series block 20 is connected to an input/output terminal 50 via a second fusible link 40. The number m of the cells 10 and the number n of the series blocks satisfy the formulas (1) and (2): m≦½[Vc/Rc·If1−Rf1/Rc+3] (1) n≧(Vc+If2·Rc)/[Vc−(m−1)If2·Rc] (2) where Vc and Rc represent an electromotive voltage and an internal resistance of the cell 10, respectively; Rf1 and If1 represent a resistance and a fuse current of the first fusible link 30, respectively; and If2 represents a fuse current of the second fusible link 40.
US09368836B2
A lithium ion rechargeable battery cell includes an anode having electroactive material-containing particles wherein the electroactive material is selective from one or more of silicon, germanium, and tin. A cathode includes an active material adapted to incorporate lithium and also to liberate lithium electrochemically. The anode is adapted to incorporate lithium during lithiation. Also provided is an electrolyte, wherein the electrolyte includes both a cyclic carbonate having a vinyl group and a fluorinated cyclic carbonate. The total amount of the cyclic carbonate including a vinyl group and the fluorinated cyclic carbonate together is in the range of 3.5 wt % to 70 wt % based on the total weight of the electrolyte solution.
US09368835B2
Disclosed are an electrolyte for a secondary battery, and a secondary battery including the same, the electrolyte including an electrolyte salt; an electrolyte solvent; and a compound generating heat through oxidation at voltages higher than drive voltage of a cathode, wherein the compound can decompose or evaporate electrolyte components by oxidation heat, thereby causing gas generation. Also, the compound is included in an internal pressure increase accelerant for a battery. Upon overcharge, since a compound subjected to oxidation at voltages higher than normal drive voltage of a cathode generates heat, electrolyte components can be decomposed or evaporated, thereby generating gas by the oxidation heat. Accordingly, it is possible to operate a safety means of a battery, without using an internal pressure increasing material directly generating gas through oxidation at overcharge voltage as the electrolyte additive, and thus to improve the overcharge safety of a secondary battery.
US09368822B2
An object of the present invention is to provide an electrolyte membrane that suppresses swelling and shrinkage caused by water retained in the electrolyte membrane for a solid polymer-type fuel cell, improves the durability of the electrolyte membrane, and obtains excellent power generation characteristics with a low resistance. The electrolyte membrane for a solid polymer-type fuel cell includes, as a reinforcing membrane, a nonwoven fabric composed of an electrolyte material and PVDF bicomponent fibers 2a, thereby improving the durability of the electrolyte membrane. Furthermore, the bicomponent fiber 2a has pores 23 that can effectively retain generated water, thereby improving battery performance under the condition of a low humidity.
US09368821B2
Disclosed is a composite electrolyte membrane for a fuel cell. The composite electrolyte membrane includes a polybenzimidazole-based polymer and a metal-grafted porous structure. The composite electrolyte membrane is doped with phosphoric acid. The metal-containing porous structure is present in an amount of 0.1 to 30% by weight, based on the weight of the polymer. The presence of the metal-containing porous structure allows the fuel cell electrolyte membrane to have excellent thermal properties and high proton conductivity.
US09368815B2
A fuel cell includes a membrane electrode assembly and a separator. The separator includes a reactant gas inlet manifold, a reactant gas outlet manifold, a reactant gas channel, an inlet connection channel, an inlet buffer portion, an outlet buffer portion, and an outlet connection channel. A pressure drop through the inlet buffer portion is less than a pressure drop through the reactant gas channel when a reactant gas flows from the reactant gas inlet manifold to the reactant gas channel. A pressure drop through the outlet buffer portion is less than a pressure drop through the outlet connection channel when the reactant gas flows from the reactant gas channel to the reactant gas outlet manifold.
US09368813B2
A fuel cell stack includes a laminated body in which a plurality of electricity generation cells are laminated and is provided with a reaction gas discharge through hole which discharges a reaction gas used in an electricity generation reaction. An end plate is arranged at one end in the lamination direction of the laminated body and is provided with a reaction gas outlet which communicates with the reaction gas discharge through hole. A drainage structure has an outlet pipe coupled to the reaction gas outlet. A tip end portion of the outlet pipe on the downstream side in the reaction gas discharge flow direction opens downward. Umbrella-shaped protrusion portions are provided within the outlet pipe. These protrusion portions have a shape which tapers toward the upstream side with respect to the reaction gas discharge flow direction, dividing the continuous flow of the discharged liquid and the reaction gas.
US09368810B2
Various embodiments include interconnects and/or end plates having features for reducing stress in a fuel cell stack. In embodiments, an interconnect/end plate may have a window seal area that is recessed relative to the flow field to indirectly reduce stress induced by an interface seal. Other features may include a thicker protective coating and/or larger uncoated area of an end plate, providing a recessed portion on an end plate for an interface seal, and/or recessing the fuel hole region of an interconnect relative to the flow field to reduce stress on the fuel cell. Further embodiments include providing intermittent seal support to minimize asymmetric seal loading and/or a non-circular seal configuration to reduce stress around the fuel hole of a fuel cell.
US09368805B2
The present invention provides a catalyst for a polymer electrolyte fuel cell including catalyst particles made of platinum supported on a carbon powder carrier, wherein the carbon powder carrier includes 0.7 to 3.0 mmol/g (based on the weight of the carrier) of a hydrophilic group bonded thereto; and the platinum particles have an average particle size of 3.5 to 8.0 nm and the platinum specific surface area based on CO adsorption (COMSA) of 40 to 100 m2/g. The catalyst for a polymer electrolyte fuel cell according to the present invention is a catalyst excellent in initial activity and satisfactory in durability.
US09368801B2
The present application relates to a spherical, porous structure which is formed using a mold taking the form of a spherical nanoparticle aggregate, and relates to a production method therefor. According to one aspect of the present application, the production method for the spherical, porous structure comprises: the use of a mold taking the form of a spherical nanoparticle-carbon precursor aggregate comprising a carbon precursor on the surfaces of a plurality of nanoparticles, formed by removing solvent from droplets comprising the carbon precursor and the plurality of nanoparticles.
US09368792B2
Disclosed are a negative active material for a rechargeable lithium battery including a spherically-shaped natural graphite-modified composite particle including: a spherically-shaped natural graphite particle where flake-shaped natural graphite fragments build up and assemble into a cabbage or random shape; and amorphous or semi-crystalline carbon, wherein an open gap between the flake-shaped natural graphite fragments is positioned on a surface part or inside the spherically-shaped natural graphite particle, the amorphous or semi-crystalline carbon is coated on the surface of the spherically-shaped natural graphite particle, and the amorphous or semi-crystalline carbon is present in the open gap, and thereby the open gap positioned on the surface part and inside the spherically-shaped natural graphite particle is maintained, a method of preparing the same, and a rechargeable lithium battery including the same.
US09368789B2
The disclosure relates to an anode material for a sodium-ion battery having the general formula AOx—C or ACx—C, where A is aluminum (Al), magnesium (Mg), titanium (Ti), vanadium (V), chromium (Cr), manganese (Mn), iron (Fe), cobalt (Co), nickel (Ni), zirconium (Zr), molybdenum (Mo), tungsten (W), niobium (Nb), tantalum (Ta), silicon (Si), or any combinations thereof. The anode material also contains an electrochemically active nanoparticles within the matrix. The nanoparticle may react with sodium ion (Na+) when placed in the anode of a sodium-ion battery. In more specific embodiments, the anode material may have the general formula MySb-M′Ox—C, Sb-MOx—C, MySn-M′Cx—C, or Sn-MCx—C. The disclosure also relates to rechargeable sodium-ion batteries containing these materials and methods of making these materials.
US09368781B2
A storage battery includes a terminal portion for storage batteries having a plurality of bolt insertion holes bored in one or a plurality of directions, a nut insertion opening through which a nut is inserted, a hollow in communication with the bolt insertion holes and the nut insertion opening and the nut having at least one screw hole threaded in a direction coincident with at least one or the plurality of directions. A fixation portion is formed to fix the nut by deforming the terminal portion with the nut being inserted through the nut insertion opening into the hollow and the at least one screw hole of the nut being in communication respectively with the at least one of the plurality of bolt insertion holes.
US09368780B2
A rechargeable battery including a pillar terminal electrically connected to a positive or negative electrode. The pillar terminal includes a first section made of a first metal, a second section made of a second metal, and a third section between the first and second sections. The third section is made of the first metal or the second metal. The third section is welded to the first section and is electroplated to the second section.
US09368776B2
A power storage device having: a laminated body formed by providing a separator layer between a first electrode which is one of a cathode and an anode and a second electrode which is the other electrode; an electrolyte; and a package which houses the laminated body and the electrolyte. At least two first electrode composite sheets are included which are each obtained by integrating a first collector electrode, a first electrode active material layer provided on one principal surface of the first collector electrode, and a separator layer covering at least part of the one principal surface, and the other principal surface of the first collector electrode of one first electrode composite sheet out of the at least two first electrode composite sheets is opposed to, and bonded to, the other principal surface of the first collector electrode of the other first electrode composite sheet.
US09368773B2
The disclosure relates to a battery cell module including a plurality of lithium ion battery cells, each having a degassing opening, and a cover substantially sealingly connected to a corresponding surface of each of the battery cells. The cover defines a gas receiving space configured to at least temporarily receive gas escaping from the battery cells. The gas receiving space is open in the direction of the battery cells. The opening area of the gas receiving space extends across a plurality of the battery cells. The disclosure further relates to a method for producing a battery cell module, to a battery, and to a motor vehicle having the battery cell module or the battery.
US09368768B1
Battery corrosive electrolyte leak is decreased by using an adjustable mechanical retention device to bias a plurality of batteries toward a first end of the series configuration wherein the adjustable mechanical retention device creates a snug mechanical fit at a bottom surface of the metal can of the terminal battery. When the device in which batteries are being used is a flashlight, a two-piece tail cap can be used, an inner member of which is driven by an outer member, and tail caps of existing flashlights can be replaced so that a strong tail cap spring no longer provides a biasing means against the terminal contact of the terminal battery.
US09368764B2
A sealed battery includes a sealing plate 13 sealing a mouth of an outer can, an external terminal 16 attached to the sealing plate 13 and having a connecting terminal 23, and a current interruption mechanism 18 interrupting current in response to pressure increase in the outer can that is installed in a conductive pathway electrically connecting the connecting terminal 23 and an electrode assembly. In the connecting terminal 23, a through-hole 23b continuing to the space on the current interruption mechanism 18 at the side corresponding to the outside of the battery is formed. The through-hole 23b is sealed with a terminal stopper 30 made of an elastic member so as to form a closed space between the terminal stopper 30 and current interruption mechanism 18. An electrolyte or washing solution hardly enters the current interruption mechanism during the manufacture can be provided.
US09368763B2
Provided is a nonaqueous electrolyte secondary battery including a bottomed cylindrical positive electrode casing and a negative electrode casing which is fixed to an opening of the positive electrode casing through a gasket. The opening of the positive electrode casing is caulked to the negative electrode casing side to seal the accommodation space. A shortest distance L1 between a caulking tip end and the negative electrode casing in the opening of the positive electrode casing is equal to or less than 70% of an average sheet thickness of the positive electrode casing, a shortest distance L2 between a tip end of the negative electrode casing and the positive electrode casing is equal to or less than 60% of the average sheet thickness of the positive electrode casing, and a distance L3 between the tip end of the negative electrode casing and the bottom of the positive electrode casing is equal to or less than 110% of the average sheet thickness of the positive electrode casing.
US09368762B2
An active organic electroluminescence device back panel and a manufacturing method thereof are disclosed. The device back panel includes: a substrate, a plurality of active TFT pixel arrays formed on the substrate, and organic planarization layers, organic electroluminescence electrodes, pixel definition layers, and support bodies formed on the active TFT pixel arrays. Each of the active TFT pixel arrays includes a driving TFT and a switch TFT. The driving TFT has a gate insulation layer that has a thickness greater than a thickness of a gate insulation layer of the switch TFT. Through thickening the gate insulation layer of the driving TFT, the gate capacitance of the driving TFT can be reduced and the sub-threshold swing of the driving TFT is increased to realize well definition of grey levels.
US09368760B2
An organic light emitting diode (OLED) display includes: a substrate including a plurality of pixels, a thin film transistor disposed in the pixels; an organic light emitting element connected to the thin film transistor and disposed in the pixels, an encapsulation member located on the organic light emitting element, and an external light blocking member disposed above or under the encapsulation member and including a first portion and a second portion. The first portion has a thickness that is thinner than a thickness of the second portion, and the first portion is disposed in the pixels.
US09368753B2
A display device includes a first substrate, a second substrate facing the first substrate, a first electrode on the first substrate, a pixel defining layer on the first substrate, the pixel defining layer including an opening corresponding to the first electrode, a light emission layer on the first electrode, a second electrode on the light emission layer, a filler between the first substrate and the second substrate, and scattering particles in the filler, the scattering particles having an average particle diameter that is less than a maximum height of the pixel defining layer.
US09368752B2
Disclosed is an organic light emitting display (OLED) device that may include first and second pixels on a substrate, each including a TFT region and a display region, the display region of each of the first and second pixels including a first electrode, an emission layer and a second electrode; a color filter layer in the display region of the second pixel; and a reflection preventing layer in the first and second pixels, substantially excluding the display region of the second pixel.
US09368751B2
An organic light-emitting display apparatus includes a thin film transistor on a display region of a substrate, the thin film transistor facing an encapsulation member, an organic light-emitting device on the display region that includes an intermediate layer having an organic emission layer, a sealing member that is between the substrate and the encapsulation member and that surrounds the display region, an internal circuit unit between the display region and the sealing member, a passivation layer that extends to cover the internal circuit unit, a pixel defining layer on the passivation layer, and a getter between the substrate and the encapsulation member, and the getter at least partially overlapping the internal circuit unit.
US09368750B1
A method for fabricating an intermediate member of an electronic element, comprises: preparing a glass substrate as a support substrate having a first surface; forming a first inorganic film that contains silicon and has a second surface and a third surface opposite to the second surface, in such a manner that the first surface of the support substrate is in contact with the second surface of the first inorganic film; forming a first polyimide film containing fluorine on the third surface of the first inorganic film; and forming a second inorganic film containing silicon on the first polyimide film.
US09368748B2
For a display device and manufacturing method for the display device, the method comprises steps of: disposing a plurality of recesses on the cover body; coating glass frit in the recesses; sintering the glass frit for forming sintered blocks; disposing display auxiliary members on the cover body having the sintered blocks formed thereon; and irradiating the sintered blocks by laser to combine the cover and the display substrate with the sintered blocks.The present invention can prevent the display auxiliary members of the cover from being damaged in the packaging process of the display device.
US09368737B2
A field-effect transistor includes a gate, a source and a drain; a semiconductor layer between the source and the drain; and a gate insulator between the gate and the semiconductor layer. The gate insulator comprises a first layer adjoining the semiconductor layer; and a second layer. The first layer is formed from an amorphous fluoropolymer having a first dielectric constant and a first thickness. The second layer has a second dielectric constant and a second thickness. The first dielectric constant is smaller than 3, the first thickness is smaller than 200 nm, the second dielectric constant is higher than 5, and the second thickness is smaller than 500 nm.
US09368732B2
To provide a novel heterocyclic compound capable of being used as a host material in which a light-emitting substance is dispersed. To provide a light-emitting element having a long lifetime. A heterocyclic compound in which a dibenzo[f,h]quinoxalinyl group and a benzo[b]naphtho[1,2-d]furanyl group are bonded through an arylene group having 6 to 13 carbon atoms. The dibenzo[f,h]quinoxalinyl group, the benzo[b]naphtho[1,2-d]furanyl group, and the arylene group separately are unsubstituted or have, as a substituent, an alkyl group having 1 to 4 carbon atoms or an aryl group having 6 to 13 carbon atoms.
US09368731B2
A top-emitting organic electroluminescence device including sequentially a first electrode, one or more organic layers comprising an emitting layer, a second electrode and a capping layer, wherein the capping layer comprises a compound represented by the following formula (1):
US09368728B2
There is provided a material for an organic electroluminescence device, which is a chrysene skeletal structure-containing diarylamine-based organic material as defined in the specification used for deposition of any layer of at least one organic layer contained in an organic electroluminescence device, wherein the water content ratio before deposition as measured by the Karl Fischer's method is from 100 to 1,000 ppm.
US09368726B2
The present invention relates to a polymer which contains at least one structural unit which has electron-transport properties, to processes for the preparation thereof and to mixtures (blends), solutions and formulations which comprise these polymers. Furthermore, the present invention relates to the use of these polymers in electronic devices, in particular in organic electro-luminescent devices, so-called OLEDs (OLED=organic light emitting diodes), and to these organic electroluminescent devices themselves. The polymers according to the invention exhibit improved efficiency, in particular on use in OLEDs.
US09368722B2
One embodiment in the present disclosure provides a resistor in a resistive random access memory (RRAM). The resistor includes a first electrode; a resistive layer on the first electrode; an electric field enhancement array in the resistive layer; and a second electrode on the resistive layer. The electric field enhancement array includes a plurality of electric field enhancers arranged in a same plane. One embodiment in the present disclosure provides a method of manufacturing a resistor structure in an RRAM. The method comprises (1) forming a first resistive layer on a first electrode; (2) forming a metal layer on the resistive layer; (3) patterning the metal layer to form a metal dot array on the resistive layer; and (4) forming a second electrode on the metal dot array. The metal dot array comprises a plurality of metal dots, and a distance between adjacent metal dots is less than 40 nm.
US09368721B1
Selector elements that can be suitable for nonvolatile memory device applications are disclosed. The selector element can have low leakage currents at low voltages to reduce sneak current paths for non-selected devices, and higher leakage currents at higher voltages to minimize voltage drops during device switching. The selector element can be based on multilayer film stacks (e.g. metal-semiconductor-metal (MSM) stacks). A structure including diamond-like carbon (DLC) can be used to surround the semiconductor layer of the MSM stack. The high thermal conductivity of the DLC structure may serve to remove heat from the selector device while higher currents are flowing through the selector element. This may lead to improved reliability and improved endurance.
US09368717B2
According to one embodiment, a magnetoresistive element is disclosed. The magnetoresistive element includes a reference layer. The reference layer includes a first region, and a second region provided outside the first region to surround the same. The second region contains an element contained in the first region and another element being different from the element. The magnetoresistive element further includes a storage layer, and a tunnel barrier layer provided between the reference layer and the storage layer. The storage layer is free from the another element.
US09368710B2
A traffic sensor includes a flexible substrate having a top surface. A piezoelectric structure extends from the first electrode layer. The piezoelectric structure has a top end. An insulating layer is infused into the piezoelectric structure. A first electrode layer is disposed on top of the insulating layer. A second electrode layer is disposed below the flexible substrate. A packaging layer is disposed around the substrate, the first electrode layer, the piezoelectric structure, the insulating layer and the second electrode layer. In a method of sensing a traffic parameter, a piezoelectric nanostructure-based traffic sensor is applied to a roadway. An electrical event generated by the piezoelectric nanostructure-based traffic sensor in response to a vehicle interacting with the piezoelectric nanostructure-based traffic sensor is detected. The electrical event is correlated with the traffic parameter.
US09368698B2
A converter plate adapted to be attached to a radiation-emitting semiconductor chip, the converter plate containing a base material made of glass in which a plurality of openings is arranged, in each of which a converter material is installed.
US09368693B2
Semiconductor structures having a nanocrystalline core and nanocrystalline shell pairing compositional transition layers are described. In an example, a semiconductor structure includes a nanocrystalline core composed of a first semiconductor material. A nanocrystalline shell composed of a second semiconductor material surrounds the nanocrystalline core. A compositional transition layer is disposed between, and in contact with, the nanocrystalline core and nanocrystalline shell and has a composition intermediate to the first and second semiconductor materials. In another example, a semiconductor structure includes a nanocrystalline core composed of a first semiconductor material. A nanocrystalline shell composed of a second semiconductor material surrounds the nanocrystalline core. A nanocrystalline outer shell surrounds the nanocrystalline shell and is composed of a third semiconductor material. A compositional transition layer is disposed between, and in contact with, the nanocrystalline shell and the nanocrystalline outer shell and has a composition intermediate to the second and third semiconductor materials.
US09368687B2
A group-III nitride semiconductor light emitting element includes a semiconductor layer that includes a light emitting layer, a p-type semiconductor layer and an n-type semiconductor layer, a p-contact electrode that is in contact with the p-type semiconductor layer, an n-contact electrode that is in contact with the n-type semiconductor layer, and a support substrate that supports the semiconductor layer. The p-contact electrode and the n-contact electrode are disposed at a position between the semiconductor layer and the support substrate. In a case where the p-contact electrode and the n-contact electrode are orthogonally projected on a plate surface of the support substrate, the p-contact electrode and the n-contact electrode are formed in a shape in which the orthogonally projected p-contact electrode and the orthogonally projected n-contact electrode are not overlapped with each other.
US09368686B2
An article, such as a light emitting device, can include a first material and a second material, wherein the first material is capable of emitting first radiation having a first emission maximum at a first wavelength, and the second material is capable of emitting second radiation in response to capturing the first radiation. The second material can have a second emission maximum at a second wavelength within the visible light spectrum. In an embodiment, the second material can be different from the first material. In another embodiment, a difference between the first wavelength and the second wavelength can be at least approximately 70 nm. Additionally, the second material can include a luminescent material having a formula of Gd3(x)Y3(1-x)Al5(y)Ga5(1-y)O12, where x is at least approximately 0.2 and no greater than approximately 0.99 and y is at least approximately 0.05 and no greater than approximately 0.99.
US09368666B2
Manufacture for an improved stacked-layered thin film solar cell. Solar cell has reduced absorber thickness and an improved back contact for Copper Indium Gallium Selenide solar cells. The back contact provides improved reflectance particularly for infrared wavelengths while still maintaining ohmic contact to the semiconductor absorber. This reflectance is achieved by producing a back contact having a highly reflecting metal separated from an absorbing layer with a dielectric layer.
US09368665B2
A solar cell module includes multiple rectangular solar cells each with chamfered corner portions, wiring members each electrically connecting adjacent ones of the solar cells to each other, and a protective member on a light-receiving surface side of the solar cells. The solar cells are arranged in matrix with spaces therebetween. The wiring member has a reflective surface in a region surrounded by the corner portions of the multiple solar cells. The reflective surface reflects light entering from the light-receiving surface side toward the protective member.
US09368662B2
A photovoltaic junction for a solar cell is provided. The photovoltaic junction has an intrinsic region comprising a multiple quantum well stack formed from a series of quantum wells separated by barriers, in which the tensile stress in some of the quantum wells is partly or completely balanced by compressive stress in the others of the quantum wells. The overall elastostatic equilibrium of the multiple quantum well stack may be ensured by engineering the structural and optical properties of the quantum wells only, with the barriers having the same lattice constant as the materials used in the oppositely doped semiconductor regions of the junction, or equivalently as the actual lattice size of the junction or intrinsic region, or the bulk or effective lattice size of the substrate. Alternatively, the barriers may contribute to the stress balance.
US09368658B2
In one embodiment, a MEMS sensor includes a mirror and an absorber spaced apart from the mirror, the absorber including a plurality of spaced apart conductive legs defining a tortuous path across an area directly above the mirror.
US09368656B2
The invention relates to a photovoltaic cell, comprising a plate shaped substrate of a semiconductor material with a solar face and a connection face, a first volume of the substrate adjacent to the solar face is doped with a first polarity, the second volume is doped with a second polarity and the volumes are separated by a pn-junction, a number of apertures in the substrate extending between both faces and in which a plug has been positioned of which a part is conducting, contact tracks at the solar face of the substrate connected with the first volume and the conducting part of the plug, first contacts at the connection face of the substrate connected with the conducting part of the plug and second contacts located at the connection face of the substrate connected with the second volume, wherein the specific electrical conductivity of the plug decreases from its centre to the contact face with the substrate.
US09368654B2
A photodetector includes a substrate and an insulating arrangement formed in the substrate. The insulating arrangement electrically insulates a confined region of the substrate. The confined region is configured to generate free charge carriers in response to an irradiation. The photodetector further includes a read-out electrode arrangement configured to provide a photocurrent formed by at least a portion of the free charge carriers that are generated in response to the irradiation. The photodetector also includes a biasing electrode arrangement that is electrically insulated against the confined region by means of the insulating arrangement. The biasing electrode arrangement is configured to cause an influence on a spatial charge carrier distribution within the confined region so that fewer of the free charge carriers recombine at boundaries of the confined region compared to an unbiased state.
US09368652B2
The present invention relates to a control device for controlling a direct current generated in a photovoltaic system. The control device is configured to alternately enable a current flow through the photovoltaic system for a first time interval and at least to reduce the current flow for a second time interval. The invention further relates to a photovoltaic system comprising such a control device as well as to a method for controlling a direct current generated in a photovoltaic system.
US09368638B2
An object is to provide a highly reliable transistor and a semiconductor device including the transistor. A semiconductor device including a gate electrode; a gate insulating film over the gate electrode; an oxide semiconductor film over the gate insulating film; and a source electrode and a drain electrode over the oxide semiconductor film, in which activation energy of the oxide semiconductor film obtained from temperature dependence of a current (on-state current) flowing between the source electrode and the drain electrode when a voltage greater than or equal to a threshold voltage is applied to the gate electrode is greater than or equal to 0 meV and less than or equal to 25 meV, is provided.
US09368633B2
An object is to provide a material suitably used for a semiconductor included in a transistor, a diode, or the like. Another object is to provide a semiconductor device including a transistor in which the condition of an electron state at an interface between an oxide semiconductor film and a gate insulating film in contact with the oxide semiconductor film is favorable. Further, another object is to manufacture a highly reliable semiconductor device by giving stable electric characteristics to a transistor in which an oxide semiconductor film is used for a channel. A semiconductor device is formed using an oxide material which includes crystal with c-axis alignment, which has a triangular or hexagonal atomic arrangement when seen from the direction of a surface or an interface and rotates around the c-axis.
US09368631B2
Disclosed is a thin film transistor including a gate electrode on a substrate. A gate dielectric layer is disposed on the gate electrode and the substrate, and source/drain electrodes are disposed on the gate dielectric layer overlying two edge parts of the gate electrode. A channel layer is disposed on the gate dielectric layer overlying a center part of the gate electrode, and the channel region contacts the source/drain electrodes. An insulating capping layer overlies the channel layer, wherein the channel layer includes an oxide semiconductor.
US09368624B2
A transistor and method of fabrication thereof includes a screening layer formed at least in part in the semiconductor substrate beneath a channel layer and a gate stack, the gate stack including spacer structures on either side of the gate stack. The transistor includes a shallow lightly doped drain region in the channel layer and a deeply lightly doped drain region at the depth relative to the bottom of the screening layer for reducing junction leakage current. A compensation layer may also be included to prevent loss of back gate control.
US09368621B1
A power semiconductor device having low on-state resistance includes a substrate having an epitaxial layer formed thereon, a gate structure, a termination structure, and a patterned conductive layer. The epitaxial layer has at least a first trench and a second trench. The gate structure is embedded in the first trench, including a gate electrode and a shielding electrode disposed under the gate electrode. The termination structure is embedded in the second trench, including a termination electrode. The patterned conductive layer is disposed above the epitaxial layer. Specially, the shield electrode of the gate structure and the termination electrode of the termination structure are configured to receive the gate voltage. The patterned conductive layer is configured to electrically contact said gate electrode and termination electrodes by a first contact plug and a second contact plug respectively.
US09368619B2
A vertical Metal-Oxide-Semiconductor (MOS) transistor includes a substrate and a nano-wire over the substrate. The nano-wire comprises a semiconductor material. An oxide ring extends from an outer sidewall of the nano-wire into the nano-wire, with a center portion of the nano-wire encircled by the oxide ring. The vertical MOS transistor further includes a gate dielectric encircling a portion of the nano-wire, a gate electrode encircling the gate dielectric, a first source/drain region underlying the gate electrode, and a second source/drain region overlying the gate electrode. The second source/drain region extends into the center portion of the nano-wire. Localized oxidation produces a local swelling in the structure that generates a tensile or compressive strain in the nano-wire.
US09368617B2
The present disclosure relates to a superjunction device and a semiconductor structure having the same. The superjunction device includes a body region of a second conduction type, a drain region of a first conduction type, a drift region located between said body region and said drain region. The drift region includes first regions of a first conduction type and second regions of a second conduction type arranged alternately along a direction being perpendicular to the direction from the body region to the drain region, and a plurality of trench gate structures, each of them comprising a trench extending into said drift region from an upper surface of said body region and a gate electrode in said trench surrounded by a first dielectric layer filling said trench, and a source region of a first conduction type embedded into said body region. There is no source region along at least 10% of the total interface length between the first dielectric layer and the body region.
US09368615B2
In one embodiment, a structure for a trench power field effect transistor device with controlled, shallow, abrupt, body contact regions.
US09368608B1
Fabrication methods for a device structure and device structures. A trench isolation region is formed that bounds an active device region of a semiconductor substrate. A first semiconductor layer is formed on the active device region and on the trench isolation region. A first airgap is formed between the first semiconductor layer and the active device region. A second airgap is formed between the first semiconductor layer and the trench isolation region. The first airgap extends into the active device region such that the height of the first airgap is greater than the height of the second airgap.
US09368602B2
Methods for fabricating an IGZO layer and fabricating TFT are provided in the present invention. The method for fabricating TFT includes the following steps: (1) depositing an IGZO layer and forming a surface oxidizing gas protective layer on the IGZO layer; (2) coating the IGZO layer with a photoresist, and then subjecting the photoresist to an exposing and developing process to form a photoresist pattern; and (3) subjecting the IGZO layer to an etching process, and then removing the photoresist. By forming an oxidizing gas protective layer, the present methods for fabricating an IGZO layer and fabricating TFT can effectively reduce the effect of hydrogen atom on IGZO layer and avoid the change of IGZO layer from semiconductor to conductor, thereby improving the stability of the IGZO layer and thus the TFT, and reducing the negative bias of threshold voltage generated by the long-term continuous use of the device.
US09368583B2
A transistor having a narrow bandgap semiconductor source/drain region is described. The transistor includes a gate electrode formed on a gate dielectric layer formed on a silicon layer. A pair of source/drain regions are formed on opposite sides of the gate electrode wherein said pair of source/drain regions comprise a narrow bandgap semiconductor film formed in the silicon layer on opposite sides of the gate electrode.
US09368582B2
An electronic device includes a III-V substrate having a hexagonal crystal structure and a normal to a growth surface characterized by a misorientation from the <0001> direction of between 0.15° and 0.65°. The electronic device also includes a first epitaxial layer coupled to the III-V substrate and a second epitaxial layer coupled to the first epitaxial layer. The electronic device further includes a first contact in electrical contact with the substrate and a second contact in electrical contact with the second epitaxial layer.
US09368579B2
A robust fabrication process for selective area growth of semiconductors in growth windows is provided. Sidewall growth is eliminated by the presence of a spacer layer which covers the sidewalls. Undesirable exposure of the top corners of the growth windows is prevented by undercutting the growth window prior to deposition of the dielectric spacer layer. The effectiveness of this process has been demonstrated by selective-area growth of Ge and Ge/SiGe quantum wells on a silicon substrate. Integration of active optoelectronic devices with waveguide layers via end-coupling through the dielectric spacer layer can be reliably accomplished in this manner.
US09368572B1
A vertical transistor has a first air-gap spacer between the gate and the bottom source/drain, and a second air-gap spacer between the gate and the contact to the bottom source/drain. A dielectric layer disposed between the gate and the contact to the top source/drain decreases parasitic capacitance and inhibits electrical shorting.
US09368570B2
An integrated circuit for a driving device is disclosed. The integrate circuit includes a substrate comprising a high-voltage area and a low-voltage area; a plurality of first trenches, formed in the high-voltage area; a plurality of first isolations, formed in the plurality of first trenches of the high-voltage area; a plurality of second trenches, formed in the low-voltage area; and a plurality of second isolations, formed in the plurality of second trenches of the low-voltage area; wherein a depth difference exists between each of the plurality of first trenches and each of the plurality of second trenches.
US09368563B2
A semiconductor device has a first semiconductor die. A first inductor is formed over the first semiconductor die. A second inductor is formed over the first inductor and aligned with the first inductor. An insulating layer is formed over the first semiconductor die and the first and second inductors. A conductive bridge is formed over the insulating layer and electrically connected between the second inductor and the first semiconductor die. In one embodiment, the semiconductor device has a second semiconductor die and a conductive layer is formed between the first and second semiconductor die. In another embodiment, a capacitor is formed over the first semiconductor die. In another embodiment, the insulating layer has a first thickness over a footprint of the first semiconductor die and a second thickness less than the first thickness outside the footprint of the first semiconductor die.
US09368528B2
A light detection device 1 has a semiconductor light detection element having a semiconductor substrate, and a mounting substrate arranged as opposed to the semiconductor light detection element. The semiconductor light detection element includes a plurality of avalanche photodiodes operating in Geiger mode and formed in the semiconductor substrate, and electrodes electrically connected to the respective avalanche photodiodes and arranged on a second principal surface side of the semiconductor substrate. The mounting substrate includes a plurality of electrodes arranged corresponding to the respective electrodes on a third principal surface side, and quenching resistors electrically connected to the respective electrodes and arranged on the third principal surface side. The electrodes and the electrodes are connected through bump electrodes.
US09368524B2
A thin film transistor array substrate including a substrate, a gate line intersecting a data line to define a pixel region on the substrate, a switching element disposed at an intersection of the gate line and the data line, a plurality of pixel electrodes and a plurality of first common electrodes alternately arranged on a protective film in the pixel region, a second common electrode overlapping the data line, a first storage electrode on the substrate, a second storage electrode overlapping the first storage electrode, and an organic insulation film on the switching element, the second storage electrode, the data line, a gate pad, and a data pad, wherein the second common electrode covers the data line, the protective film and the organic insulation film, and has inclined surfaces connected to the protective film within the pixel region.
US09368522B2
A display device is disclosed which includes: gate lines and data lines crossing each other to define unit pixel regions in a display area; a pixel electrode in each unit pixel region; a data shorting bar in a non-display area in substantially parallel with the gate lines; a gate shorting bar in the non-display area in substantially parallel with the data lines; gate link lines electrically connecting the gate lines to the gate shorting bar; data link lines electrically connecting the data lines to the data shorting bar; and shield electrodes on at least one of the gate link lines and the data link lines, the shield electrodes including a conductive material that has a higher melting temperature than that of the at least one of the gate link lines and the data link lines.
US09368506B2
Integrated circuits and methods for fabricating integrated circuits are provided. In an exemplary embodiment, an integrated circuit includes a semiconductor substrate doped with a first conductivity-determining impurity. The semiconductor substrate has formed therein a first well doped with a second conductivity-determining impurity that is different from the first conductivity-determining impurity, a second well, formed within the first well, and doped with the first conductivity-determining impurity, and a third well spaced apart from the first and second wells and doped with the first conductivity-determining impurity. The integrated circuit further includes a floating gate structure formed over the semiconductor substrate. The floating gate structure includes a first gate element disposed over the second well and being separated from the second well with a dielectric layer, a second gate element disposed over the third well and being separated from the third well with the dielectric layer, and a conductive connector.
US09368501B2
A semiconductor memory device which includes a memory cell including two or more sub memory cells is provided. The sub memory cells each including a word line, a bit line, a first capacitor, a second capacitor, and a transistor. In the semiconductor device, the sub memory cells are stacked in the memory cell; a first gate and a second gate are formed with a semiconductor film provided therebetween in the transistor; the first gate and the second gate are connected to the word line; one of a source and a drain of the transistor is connected to the bit line; the other of the source and the drain of the transistor is connected to the first capacitor and the second capacitor; and the first gate and the second gate of the transistor in each sub memory cell overlap with each other and are connected to each other.
US09368497B2
A method for fabricating fin field-effect transistors includes providing a semiconductor substrate; and forming a plurality of fins on a surface of the semiconductor substrate. The method also includes forming dummy gates formed over side and top surfaces of the fins; forming a precursor material layer with a surface higher than top surfaces of the fins to cover the dummy gates and the semiconductor substrate; performing a thermal annealing process to convert the precursor material layer into a dielectric layer having a plurality of voids; and planarizing the dielectric layer to expose the top surfaces of the dummy gates. Further, the method also includes performing a post-treatment process using oxygen-contained de-ionized water on the planarized dielectric layer to eliminate the plurality of voids formed in the dielectric layer; removing the dummy gates to form trenches; and forming a high-K metal gate structure in each of the trenches.
US09368496B1
Methods for creating uniform source/drain cavities filled with uniform levels of materials in an IC device and resulting devices are disclosed. Embodiments include forming a hard mask on an upper surface of a Si substrate, the hard mask having an opening over a STI region formed in the Si substrate and extending over adjacent portions of the Si substrate; forming low-k dielectric spacers on a lower portion of sidewalls of the opening, the spacers being formed between the sidewalls and the STI region; filling the opening with an oxide; removing the hard mask; removing an upper portion of the oxide and a portion of the low-k dielectric spacers; revealing a Si fin in the Si substrate; forming equally spaced gate electrodes, each having sidewall spacers, over the Si fin and the oxide; and forming source/drain regions in the Si fin between each pair of adjacent gate electrodes.
US09368488B2
Device and methods for forming a device are presented. The method includes providing a substrate. The substrate includes a resistor region defined by a resistor isolation region. A resistor gate is formed on the resistor isolation region. An implant mask with an opening exposing the resistor region is formed. Resistor well dopants are implanted to form a resistor well in the substrate. The resistor well is disposed in the substrate below the resistor isolation region. Resistor dopants are implanted into the resistor gate to define the sheet resistance of the resistor gate. Terminal dopants are implanted to form first and second resistor terminals at sides of the resistor gate. A central portion of the resistor gate sandwiched by the resistor terminals serves as a resistive portion.
US09368487B1
An electrostatic discharge (ESD) protection device is disclosed, which includes a substrate of a positive dopant type; a p-well defined in the substrate; a depletion inducing structure of a negative dopant type having a gap defined in a bottom portion thereof disposed in the p-well, and a n-channel device disposed in a planar encircled region defined by the depletion inducing structure. The well region is in connection with the substrate through the depletion inducing structure. Upon an ESD stress, the depletion inducing structure induces an expanded depletion region in the substrate under the well region, thus providing a substrate trigger mechanism that reduces the triggering voltage of the ESD protection device.
US09368484B1
A fin type ESD protection device includes at least one first fin, at least one second fin, and at least one gate structure. The first fin is disposed on a semiconductor substrate, and a source contact contacts the first fin. The second fin is disposed on the semiconductor substrate, and a drain contact contacts the second fin. The first fin and the second fin extend in a first direction respectively, and the first fin is separated from the second fin. The gate structure is disposed between the source contact and the drain contact. The first fin is separated from the drain contact, and the second fin is separated from the source contact.
US09368477B2
A circuit panel can include contacts exposed at a connection site of a major surface thereof and configured to be coupled to terminals of a microelectronic package. The connection site can define a peripheral boundary on the major surface surrounding a group of the contacts that is configured to be coupled to a single microelectronic package. The group of contacts can include first, second, third, and fourth sets of first contacts. Signal assignments of the first and third sets of first contacts can be symmetric about a theoretical plane normal to the major surface with signal assignments of the respective second and fourth sets of first contacts. Each of the sets of first contacts can be configured to carry identical signals. Each of the sets of first contacts can be configured to carry address information sufficient to specify a location within a memory storage array of the microelectronic package.
US09368475B2
A manufacturing method of a semiconductor device is provided. First, a mould is provided. The mould has a chamber, patterns in the chamber, and protrusions in the chamber. A carrier substrate having at least one die located thereon is disposed in the chamber, and the protrusions surround the die. A thermosetting material is injected into the chamber and is cured. The cured thermosetting material is separated from the mould, so as to form an interposer substrate. A plurality of through holes corresponding to the protrusions and a plurality of grooves corresponding to the patterns are formed on the interposer substrate. A conductive material is filled into the through holes and the grooves to form a plurality of conductive pillars and a first conductive pattern layer on a first surface of the interposer substrate. The first conductive pattern layer is electrically connected with the conductive pillars.
US09368472B2
The invention relates to a flip-chip assembly process for connecting two microelectronic components (1, 2) to each other. According to the invention, it is possible either to proportion the spacers (24) so that they are smaller than the interconnect bumps (22) or to oversize the latter so that their deformation, after having been plastic during the insertion of connective inserts (12), returns to the elastic regime once assembly contact between components (1,2) has been reached. Thanks to the invention, it is possible to control with great precision the gap between the two components during their assembly, and this without adding any additional steps to their manufacturing or to the assembly process.
US09368468B2
An integrated circuit assembly includes an insulating layer having a having a first surface and a second surface, where the first surface of the insulating layer is less than 10 microns below an upper plane of the integrated circuit assembly. An active layer contacts the first surface of the insulating layer. A metal bond pad is electrically connected to the active layer and formed on the second surface of the insulating layer, and is also electrically connected to a printed circuit board.
US09368466B2
A bump contact electrically connects a conductor on a substrate and a contact pad on a semiconductor device mounted to the substrate. The first end of an electrically conductive pillar effects electrical contact and mechanical attachment of the pillar to the contact pad with the pillar projecting outwardly from the semiconductor device. A solder crown reflowable at a predetermined temperature into effecting electrical contact and mechanical attachment with the conductor is positioned in axial alignment with the second end of the pillar. A diffusion barrier electrically and mechanically joins the solder bump to the second end of the pillar and resists electro-migration into the first end of the solder crown of copper from the pillar. One diffusion barrier takes the form of a 2-20 micron thick control layer of nickel, palladium, titanium-tungsten, nickel-vanadium, or tantalum nitride positioned between the pillar and the solder crown.
US09368465B2
The method includes forming an upper layer on a lower layer, forming a metal interconnection in the upper layer, forming a passivation layer exposing a center part of the metal interconnection on the upper layer, forming a buffer pattern exposing the center part of the metal interconnection, and selectively and asymmetrically covering a peripheral region of the metal interconnect and a part of the passivation layer, forming a wrapping pattern covering the buffer pattern and exposing the center part of the metal interconnection on the passivation layer, and forming a pad pattern on the center part of the metal interconnection.
US09368458B2
A semiconductor package includes an interposer chip having a frontside, a backside, and a corner area on the backside defined by a first corner edge and a second corner edge of the interposer chip. A die is bonded to the frontside of the interposer chip. At least one dam structure is formed on the corner area of the backside of the interposer chip. The dam structure includes an edge aligned to at least one the first corner edge and the second corner edge of the interposer chip.
US09368445B2
Provided is an e-fuse structure of a semiconductor device. the e-fuse structure may include a fuse link formed of a first metal material to connect a cathode with an anode, a capping dielectric covering a top surface of the fuse link, and a dummy metal plug penetrating the capping dielectric and being in contact with a portion of the fuse link. The dummy metal plug may include a metal layer and a barrier metal layer interposed between the metal layer and the fuse link. The barrier metal layer may be formed of a second metal material different from the first metal material.
US09368435B2
In an embodiment, an electronic component includes a dielectric layer, a semiconductor device embedded in the dielectric layer, an electrically conductive substrate, a redistribution layer having a first surface and a second surface providing at least one outer contact, and a first electrically conductive member. The semiconductor device has a first surface including at least one first contact pad and a second surface including at least one second contact pad. The second contact pad is mounted on the electrically conductive substrate. The first electrically conductive member includes at least one stud bump and extends between the electrically conductive substrate and the first surface of the redistribution layer.
US09368429B2
Integration of sensor chips with integrated circuit (IC) chips. At least a first sensor chip including a first sensor is affixed to a first side of an interposer to hermitically seal the first sensor within a first cavity. An IC chip is affixed to a second side of the interposer opposite the first sensor, the IC chip is electrically coupled to the first sensor by a through via in the interposer. In embodiments, the first sensor includes a MEMS device and the IC chip comprises a circuit to amplify a signal from the MEMS device. The interposer may be made of glass, with the first sensor chip and the IC chip flip-chip bonded to the interposer by compression or solder. Lateral interconnect traces provide I/O between the devices on the interposer and/or a PCB upon which the interpose is affixed.
US09368427B2
An integrated circuit film and a method of manufacturing the same are disclosed. The integrated circuit film includes a circuit board containing a circuit route; a first set of pads located on a first surface of the circuit board and configured to be applicable to ISO 7816 standard; and a semiconductor device mounted on the circuit board for communicating with at least one of the first set of pads. The first set of pads are arranged in two rows and the semiconductor device is mounted on the circuit board in a space between the two rows of pads.
US09368423B2
A semiconductor device has a substrate including a base and a plurality of conductive posts extending from the base. A semiconductor die is disposed on a surface of the base between the conductive posts. An interconnect structure is formed over the semiconductor die and conductive posts. An adhesive layer is disposed over the semiconductor die. A conductive layer is disposed over the adhesive layer. An encapsulant is deposited over the semiconductor die and around the conductive posts. One or more conductive posts are electrically isolated from the substrate. The conductive layer is a removable or sacrificial cap layer. The substrate includes a wafer-shape, panel, or singulated form. The semiconductor die is disposed below a height of the conductive posts. An interconnect structure is formed over the semiconductor die, encapsulant, and conductive posts.
US09368422B2
One embodiment sets forth an integrated circuit package that includes a substrate, one or more devices mounted on the substrate, a layer of under-fill configured to secure the one or more devices on the substrate, and a solder trench formed in the substrate, where the aggregate volume of the solder trench is large enough to capture a flow of excess under-fill during fabrication. One advantage of the disclosed integrated circuit package is that the solder trench is used in lieu of solder dam structures, thereby allowing a stencil to be lowered closer to the substrate surface during fabrication, which facilitates depositing solder paste during fabrication.
US09368420B2
Fabrication methods are disclosed that facilitate the production of electronic structures that are both flexible and stretchable to conform to non-planar (e.g. curved) surfaces without suffering functional damage due to excessive strain. Electronic structures including CMOS devices are provided that can be stretched or squeezed within acceptable limits without failing or breaking. The methods disclosed herein further facilitate the production of flexible, stretchable electronic structures having multiple levels of intra-chip connectors. Such connectors are formed through deposition and photolithographic patterning (back end of the line processing) and can be released following transfer of the electronic structures to flexible substrates.
US09368417B2
A system and method for testing electrical connections is provided. In an embodiment one or more floating pads may be manufactured in electrical connection with an underbump metallization structure. A test may then be performed to measure the electrical characteristics of the underbump metallization structure through the floating pad in order to test for defects. Alternatively, a conductive connection may be formed on the underbump metallization and the test may be performed on the conductive connection and the underbump metallization together.
US09368416B2
A binning process uses curve fitting to create and assign one or more bins based on testing data of operating voltage versus leakage current for test integrated circuits. Each bin is created by assigning an initial operating voltage to the bin and fitting a curve to the testing data population. An equation is generated describing the fitted curve. Integrated circuits are binned by measuring the leakage current at a selected operating voltage and testing the integrated circuit at one or more operating voltages determined based on the fitted curves. The integrated circuits are assigned a maximum operating voltage that corresponds to the lowest tested operating voltage at which the integrated circuit passes the test.
US09368410B2
A semiconductor device and method of manufacturing is disclosed which has a tensile and/or compressive strain applied thereto. The method includes forming at least one trench in a material; and filling the at least one trench by an oxidation process thereby forming a strain concentration in a channel of a device. The structure includes a gate structure having a channel and a first oxidized trench on a first of the channel, respectively. The first oxidized trench creates a strain component in the channel to increase device performance.
US09368409B2
The present disclosure provides a method for fabricating semiconductor devices. The method includes providing a substrate with a gate electrode film on the substrate and a gate electrode pattern film on the gate electrode film; forming at least one pattern layer on the gate electrode pattern film; and using the at least one pattern layer as the etch mask to etch portions of the gate electrode pattern film to expose portions of the gate electrode film and form a gate electrode pattern layer on the gate electrode film, the gate electrode pattern layer including a hard mask layer and a silicon layer, and sidewalls of the silicon layer in a direction perpendicular to a first direction having a first poly line width roughness. The method also includes performing an etch-repairing treatment on the sidewalls of the silicon layer in the direction perpendicular to the first direction.
US09368408B2
A semiconductor device includes a source zone of a first conductivity type formed in a first electrode fin that extends from a first surface into a semiconductor portion. A drain region of the first conductivity type is formed in a second electrode fin that extends from the first surface into the semiconductor portion. A channel/body zone is formed in a transistor fin that extends between the first and second electrode fins at a distance to the first surface. The first and second electrode fins extend along a first lateral direction. A width of first gate sections, which are arranged on opposing sides of the transistor fin, along a second lateral direction perpendicular to the first lateral direction is greater than a distance between the first and second electrode fins.
US09368404B2
The present invention provides a method for dicing a substrate with back metal, the method comprising the following steps. The substrate is provided with a first surface and a second surface wherein the second surface is opposed to the first surface. A mask layer is provided on the first surface of the substrate and a thin film layer is provided on the second surface of the substrate. The first surface of the substrate is diced through the mask layer to expose the thin film layer on the second surface of the substrate. A fluid from a fluid jet is applied to the thin film layer on the second surface of the substrate after the thin film layer has been exposed by the dicing step.
US09368395B1
Provided are approaches for forming a self-aligned via and an air gap within a semiconductor device. Specifically, one approach produces a device having: a first metal line beneath a second metal line within an ultra low-k (ULK) dielectric, the first metal line connected to the second metal line by a first via; a dielectric capping layer formed over the second metal line; a third metal line within first and second via openings formed within a ULK fill material formed over the dielectric capping layer, wherein the third metal line within the first via opening extends to a top surface of the dielectric capping layer, and wherein the third metal line within the second via opening is connected to the second metal by a second via passing through the dielectric capping layer; and an air gap formed between the third metal line within the first and seconds via openings.
US09368390B2
A method for fabricating a semiconductor apparatus including providing a first silicon substrate having a first contact, wherein providing the first silicon substrate comprises forming a silicide layer between the first silicon substrate and a first metal layer. The method further includes providing a second silicon substrate having a second contact comprising a second metal layer and placing the first contact in contact with the second contact. The method further includes heating the first and second metal layers to form a metallic alloy, whereby the metallic alloy bonds the first contact to the second contact.
US09368387B2
A method of forming a shallow trench isolation (STI) structure in a substrate includes forming a pad oxide layer over the substrate. The method includes forming a nitride-containing layer over the pad oxide layer, wherein the nitride-containing layer has a first thickness. The method further includes forming the STI structure extending through the nitride-containing layer, into the substrate. The STI structure has a height above a top surface of the pad oxide layer. The method includes establishing a correlation between the first thickness, the height of the STI structure above the top surface of the pad oxide layer, and an offset between the first thickness and the height of the STI structure above the top surface of the pad oxide layer. The method includes calculating the height of the STI structure above the pad oxide layer based on the correlation, and selectively removing a determined thickness of the STI structure.
US09368385B2
A method for manufacturing a semiconductor integrated circuit device includes the step of forming an SOI device region and a bulk device region on an SOI type semiconductor wafer. The method includes: removing a BOX layer and an SOI layer in a bulk device region; and thereafter forming an STI region in both the SOI device region and the bulk device region. In the method, the STI region in the SOI device region is formed to extend through the BOX layer.
US09368384B2
A substrate conveying method conveying a layered body having first and second substrates stacked with a spacer member provided between their respective bottom surfaces facing each other includes receiving the first substrate by holding the first substrate from below its bottom surface using a first holding mechanism provided on a side of a first fork provided above a second fork, and turning the first fork upside down and placing the received first substrate on the second fork; receiving the spacer member held in a substrate holding part by holding the spacer member from above using a second holding mechanism provided on the same side of the first fork as the first holding mechanism, and placing the received spacer member on the first substrate; and holding the second substrate from above its top surface using the first holding mechanism, and placing the received second substrate on the spacer member.
US09368379B2
A system and method of controlling a semiconductor wafer fabrication process. The method includes positioning a semiconductor wafer on a wafer support assembly in a wafer processing module. A signal is transmitted from a signal emitter positioned at a predetermined transmission angle relative to an axis normal to the wafer support assembly to check leveling of the wafer in the module, so that the signal is reflected from the wafer. The embodiment includes monitoring for the reflected signal at a predetermined reflectance angle relative to the axis normal to the wafer support assembly at a signal receiver. A warning indication is generated if the reflected signal is not received at the signal receiver.
US09368377B2
The present invention provides a temperature control unit for an electrostatic adsorption electrode that is capable of controlling the wafer temperature rapidly over a wide temperature range without affecting in-plane uniformity while high heat input etching is conducted with high wafer bias power applied. A refrigerant flow path provided in the electrostatic adsorption electrode serves as an evaporator. The refrigerant flow path is connected to a compressor, a condenser, and a first expansion valve to form a direct expansion type refrigeration cycle. A second expansion valve is installed between the electrostatic adsorption electrode and the compressor to adjust the flow rate of a refrigerant. This makes it possible to compress the refrigerant in the refrigerant flow path of the electrostatic adsorption electrode and adjust the wafer temperature to a high level by raising the refrigerant evaporation temperature. Further, a thin-walled cylindrical refrigerant flow path is employed so that the thin-walled cylinder is deformed only slightly by the refrigerant pressure.
US09368376B2
A mechanical debonding method and system are provided. A mechanical debonding method, used to debond temporary bonding wafers formed by bonding a device wafer and a carrier wafer by an adhesive, includes: obtaining the height position of the adhesive through a thickness measurement apparatus; moving a cutting apparatus to a position between the device wafer and the carrier wafer based on the height position of the adhesive, then removing the adhesive at the edge of the temporary bonding wafers by the cutting apparatus; removing the carrier wafer from the temporary bonding wafers; cleaning the adhesive left on the surface of the device wafer.
US09368369B2
In some embodiments methods of processing a substrate include: providing a substrate having a contact structure formed on the substrate, wherein the contact structure comprises a feature defined by gate structures, a silicon nitride layer disposed on a upper surface of the gate structures and on sidewalls and a bottom of the feature, and an oxide layer disposed over the silicon nitride layer and filling the feature; etching an opening through the oxide layer to the silicon nitride layer disposed on the bottom of the opening, wherein a width of the opening is less than a width of the feature; expanding the opening in the oxide layer to form a tapered profile; exposing the substrate to ammonia and nitrogen trifluoride to form an ammonium fluoride gas that forms an ammonium hexafluorosilicate film on the oxide layer; and heating the substrate to a second temperature to sublimate the ammonium hexafluorosilicate film.
US09368366B2
A method of forming a plurality of regularly spaced lithography features, the method including providing a self-assemblable block copolymer having first and second blocks in a plurality of trenches on a substrate, each trench including opposing side-walls and a base, with the side-walls having a width therebetween, wherein a first trench has a greater width than a second trench; causing the self-assemblable block copolymer to self-assemble into an ordered layer in each trench, the layer having a first domain of the first block alternating with a second domain of the second block, wherein the first and second trenches have the same number of each respective domain; and selectively removing the first domain to form regularly spaced rows of lithography features having the second domain along each trench, wherein the pitch of the features in the first trench is greater than the pitch of the features in the second trench.
US09368362B2
Methods of forming a semiconductor device are provided. A method of forming a semiconductor device may include forming a capping layer on a metal pattern and on an adjacent portion of an insulating layer, the capping layer comprising a first etch selectivity, with respect to the insulating layer, on the metal pattern and a second etch selectivity, with respect to the insulating layer, on the portion of the insulating layer. Moreover, the method may include forming a recess region adjacent the metal pattern by removing the capping layer from the portion of the insulating layer. At least a portion of the capping layer may remain on an uppermost surface of the metal pattern after removing the capping layer from the portion of the insulating layer. Related semiconductor devices are also provided.
US09368361B2
In one embodiment, a method for forming an electronic device includes providing a substrate having a plurality of electronic devices formed therein, forming a protective layer over a major surface of the substrate containing the plurality of electronic devices, forming a mold layer over the protective layer, thinning a major surface of the substrate opposite to the major surface containing the plurality of electronic devices, and removing the adhesive layer and the mold layer. In another embodiment, a zone coating layer can be included between the protective layer and the mold layer.
US09368358B2
A method of manufacturing a semiconductor device includes: (a) supplying a halogen-based source gas containing a first element to a substrate; (b) supplying a reaction gas containing a second element to react with the first element to the substrate; (c) forming a first layer containing the first element and the second element by time-dividing and performing (a) and (b) a predetermined number of times; (d) supplying an organic source gas containing the first element to the substrate; (e) supplying the reaction gas to the substrate; (f) forming a second layer containing the first element and the second element by time-dividing and performing (d) and (e) a predetermined number of times; and (g) forming a thin film containing the first element and the second element on the substrate by time-dividing and performing (c) and (f) a predetermined number of times.
US09368357B2
A method includes etching a dielectric layer to form an opening, with an underlying region underlying the dielectric layer exposed to the opening, and performing a bombardment to bombard a surface region of the underlying region through the opening. After the bombardment, the surface region is reacted with a process gas to form a reaction layer. An anneal is then performed to remove the reaction layer.
US09368349B2
The present disclosure relates to a method of performing a self-aligned litho-etch (SALE) process. In some embodiments, the method is performed by forming a spacer material over a substrate having a multi-layer hard mask with a first layer and an underlying second layer to provide a first cut layer, and forming a reverse material over the spacer material to form a second cut layer. A second plurality of openings, cut according to the second cut layer, are formed to expose the second layer at a positions corresponding to a second plurality of shapes of a SALE design layer. A first plurality of openings, cut according to the first cut layer, are formed to expose the second layer at a positions corresponding to a first plurality of shapes of the SALE design layer. The second layer is etched according to the first and second plurality of openings.
US09368345B2
A step of preparing a silicon carbide substrate, a step of forming a first silicon carbide semiconductor layer on the silicon carbide substrate using a first source material gas, and a step of forming a second silicon carbide semiconductor layer on the first silicon carbide semiconductor layer using a second source material gas are provided. In the step of forming a first silicon carbide semiconductor layer and the step of forming a second silicon carbide semiconductor layer, ammonia gas is used as a dopant gas, and the first source material gas has a C/Si ratio of not less than 1.6 and not more than 2.2, the C/Si ratio being the number of carbon atoms to the number of silicon atoms.
US09368332B2
A microchannel plate includes a substrate defining a plurality of channels extending from a top surface of the substrate to a bottom surface of the substrate. A resistive layer is formed over an outer surface of the plurality of channels that provides ohmic conduction with a predetermined resistivity that is substantially constant. An emissive layer is formed over the resistive layer. A top electrode is positioned on the top surface of the substrate. A bottom electrode positioned on the bottom surface of the substrate.
US09368329B2
A synchronized pulsing arrangement for providing at least two synchronized pulsing RF signals to a plasma processing chamber of a plasma processing system is provided. The arrangement includes a first RF generator for providing a first RF signal. The first RF signal is provided to the plasma processing chamber to energize a plasma therein, the first RF signal representing a pulsing RF signal. The arrangement also includes a second RF generator for providing a second RF signal to the plasma processing chamber. The second RF generator has a sensor subsystem for detecting values of at least one parameter associated with the plasma processing chamber that reflects whether the first RF signal is pulsed high or pulsed low and a pulse controlling subsystem for pulsing the second RF signal responsive to the detecting the values of at least one parameter.
US09368320B2
The purpose of the present invention is to provide a stage apparatus that effectively suppresses the transmission of heat generated by a drive mechanism to a sample, and a charged particle beam apparatus using the same. In order to achieve the purpose, there are proposed a stage apparatus and a charged particle beam apparatus. The stage apparatus comprises a table; a drive source that drives the table in a predetermined direction; a first connection member provided between the table and the drive source; a second connection member provided between the table and the drive source and closer to the drive source than the first member; a slide unit supported by the second connection member; and a rail guiding the slide unit in a predetermined direction, the first connection member comprising a member having a relatively low heat conductivity with respect to the second connection member.
US09368317B2
A rotating anode disk is balanced in a state where the rotating anode disk is mounted inside an X-ray tube. An adjustment device (54) balances the rotating anode disk in an operating state. The adjustment device includes at least a first plurality (72) of balancing elements (74) which are attached to at least one circular ring structure (76). The balancing elements each include a balancing portion (80) mounted to the circular ring structure via a bending portion (82). The bending portions are configured to be heated to a bending temperature to allow a radial pivoting movement (84) of the balancing portion from a first state (86) into a second state (88) caused by centrifugal forces upon rotation. A center of mass of the balancing portion is closer to a center (90) of the circular ring structure in a first state than the second state.
US09368315B2
A steak tube has a container with an entrance plate and an output plate, a photocathode disposed in the container and configured to emit electrons according to light to be measured, the light having been incident through the entrance plate, and a sweep electrode disposed in the container, having a pair of deflection plates for generating an electric field and a connection lead connected to each deflection plate, and configured to sweep the electrons in a sweep direction along the output plate. An opposing of edges of the deflection plate in a direction of the output plate are formed so as to extend in a direction from the entrance plate to the output plate, the connection lead has a first connection portion electrically connected to the deflection plate, and the first connection portion is connected to the opposing of edges.
US09368308B2
In order to produce a cost-effective fuse in chip design, which is applied to a carrier substrate made of a Al2O3 ceramic having a high thermal conductivity, and which is provided with a fusible metallic conductor and a cover layer, in which the melting point of the metallic conductor may be defined reliably, it is suggested that an intermediate layer having low thermal conductivity be positioned between the carrier substrate and the metallic conductor, the intermediate layer being formed by a low-melting-point inorganic glass paste applied in the screen-printing method or an organic intermediate layer applied in island printing. Furthermore, a method for manufacturing the fuse is specified.
US09368307B2
A safety switching device for fail-safely switching on and off an electrical load, and to a system comprising at least two safety switching devices which interact in a fail-safe manner via a single-channel. The safety switching device comprises a fail-safe control unit, a first and a second electronic switching element connected with a first and a second output terminal; and at least one input terminal for receiving a first switching signal that causes a switching of said switching elements. Said first and second switching elements each comprise an output which provides depending on the first switching signal an output signal having a first or second potential. A third output terminal connects said safety switching device to a second safety switching device, providing a clocked signal depending on the first switching signal and being monitored by said control unit for performing a cross fault detection.
US09368299B1
A thin keyboard depressing structure includes a circuit board and a frame. The circuit board includes a plurality of trigger portions each can be triggered to generate a keyboard signal. The frame is stacked over the circuit board and forms an outer frame, a plurality of inner frames and a plurality of keycaps in an integrated manner. The outer frame has a plurality of holding zones corresponding to the trigger portions. Each keycap is held in one holding zone corresponding to one trigger portion. The outer frame and the keycap are bridged by one inner frame. Each inner frame has at least two first connecting portions connected to the outer frame and at least two second connecting portions connected to the keycap. Each first connecting portion and each second connecting portion are bridged by a support portion.
US09368298B2
A switch includes a case, fixed electrodes, a movable electrode and a pressing member. The fixed electrodes and the movable electrode are arranged inside the recess. The pressing member is arranged so as to cover at least a part of the recess, and displaces the movable electrode from the second position to the first position by a pressing force from the outside. The pressing member includes a first bent part and a second bent part, and a deforming part disposed therebetween. The deforming part is opposed to the movable electrode with a gap in a state where the movable electrode is in the second position. The deforming part is configured to be flexibly deformed toward the outside of the case in a state where the movable electrode is in the first position in which the fixed electrodes are in a conductive state.
US09368296B2
A fusible switch assembly including a line base assembly and load base assembly is disclosed. Line base assembly includes a low-profile fuse clip assembly and line bus connector assembly with single-piece connector body and sliding nuts. Load base assembly includes a fuse clip and lug assembly having a lug body including a multiple lugs and a fuse clip at least partially formed by the lug body. Line base assemblies, load base assemblies, fuse clip assemblies, line bus connector assemblies, fuse clip and lug assemblies, and methods of operating line base assemblies are provided, as are other aspects.
US09368294B2
A solenoid operated device includes: a fixed iron core formed of a horizontal iron core portion and vertical iron core portions; a movable iron core disposed in an axially displaceable manner with respect to the fixed iron core; a magnet coil disposed between the movable iron core and the vertical iron core portions of the fixed iron core; and a drive shaft installed at an axial center portion of the movable iron core and driving a switchgear to open and close a switch thereof. The solenoid operated device is provided with a stopper installed on the drive shaft in a shaft portion penetrating through the horizontal iron core portion of the fixed iron core and regulating an opening direction position of the movable iron core by abutting on the horizontal iron core portion of the fixed iron core during an opening operation of the switchgear.
US09368279B2
An electronic part that includes an electronic part main body and an external electrode on the surface of the electronic part main body. The external electrode includes at least one alloy layer selected from among a Cu—Ni alloy layer and a Cu—Mn alloy layer, and a Sn-containing layer on the outer side of the alloy layer. The Sn-containing layer is the outermost layer of the external electrode. The Sn-containing layer is in contact with the alloy layer.
US09368277B2
Provided is a method for producing an RFeB-based magnet, the method including: disposing a nozzle so as to be opposed to an attachment surface of a base material that is a sintered magnet or hot-plastic worked magnet composed of an RFeB-based magnet containing a light rare earth element RL that is at least one element selected from the group consisting of Nd and Pr, Fe, and B; ejecting a mixture, from the nozzle, obtained by mixing an organic solvent and an RH-containing powder containing a heavy rare earth element RH that is at least one element selected from the group consisting of Dy, Tb and Ho so as to attach the mixture to the attachment surface; and heating the base material together with the mixture.
US09368270B2
A planar transformer assembly, for use in charging capacitors of an ICD, includes windings arranged to minimize voltage across intervening dielectric layers. Each secondary winding of a preferred plurality of secondary windings is arranged relative to a primary winding, in a hierarchical fashion, such that the DC voltage, with respect to ground, of a first secondary winding, of the plurality of secondary windings, is lower than that of a second secondary winding, with respect to ground, wherein the first secondary winding is in closest proximity to the primary winding. The primary winding and each secondary winding are preferably formed on a corresponding plurality of dielectric layers.
US09368263B2
A magnet assembly, having a disk-shaped magnet, which is made predominantly of metal material and has a through-hole and, by the through-hole, can be placed onto a region of a shaft made of plastic by a press fit. In the region of the magnet placed onto the shaft, the shaft has a diameter that is smaller than the diameter of the through-hole. The shaft has a plurality of radially protruding projections in the region of the magnet placed onto the shaft. The projections are distributed evenly on the circumference of the shaft and, with respect to the longitudinal axis of the shaft, having a radius, the double of which is oversized relative to the diameter of the through-hole before the magnet is placed onto the projections of the shaft.
US09368252B2
A method for forming a vapor-grown graphite fibers (VGGF) composition and a VGGF composition formed by the method are provided. In this method, a transition metal compound catalyst and three organic co-catalysts are mixed with a hydrocarbon compound, and then are delivered into a tubular reactor and pyrolized and graphitized to produce the VGGF composition. The VGGF composition includes a carbon ingredient containing a carbon content of at least 99.9 wt %. The carbon ingredient has a graphitization degree of at least 75%, and the carbon ingredient includes non-fibrous carbon and fibrous VGGF, wherein an area ratio of the non-fibrous carbon to the fibrous VGGF is about equal to or smaller than 5%. The fibrous VGGF include graphite fibers having a 3-D linkage structure, wherein the content of the graphite fibers having the 3-D linkage structure in the fibrous VGGF is about between 5 area % and 50 area %.
US09368251B2
A multilayer ceramic capacitor includes a ceramic body including dielectric layers and internal electrodes, electrode layers connected to the internal electrodes, and a conductive resin layer formed on the electrode layer and containing conductive particles, fullerenes, and a base resin.
US09368248B2
A method for making a nanowire-based electrode having homogenous optical property and heterogeneous electrical property is disclosed. The method comprises forming a pattern on the electrode using a photolytically process.
US09368246B2
The invention relates to a control device (10) comprising a radiation source (17) which is embodied, in particular, as an X-ray source for irradiating a pharmaceutical product (1) embodied, in particular as a capsule, a detector (18) for detecting radiation after irradiating the pharmaceutical product (1), a tube or shaft-shaped supply device (15) which is preferably arranged vertically at least in the region of the beam path (16) of the radiation source (17) for feeding the pharmaceutical product (1) into the beam path (16) of the radiation source (17), and means (25) for positioning and releasing the pharmaceutical product (1) in the region of the radiation beam (16) of the radiation source (17). According to the invention, the tube or shaft-shaped supply device (15) has a cross-section in the region of the beam path (16) which is greater than the cross-section of the pharmaceutical product (1), and that during irradiation, respectively only one pharmaceutical product (1) is arranged in the region of the beam path (16) of the radiation source (17).
US09368243B2
A process for encapsulating a radioactive object to render the object suitable for shipment and/or storage, and including the steps of preparing a plastic material, causing the plastic material to react with a foaming agent, generating a foaming plastic, encapsulating the radioactive object in the foaming plastic, and allowing the foaming plastic to solidify around the radioactive object to form an impervious coating.
US09368238B2
Example embodiments provide a Basemat-Internal Melt Arrest and Coolability device (BiMAC) that offers improved spatial and mechanical characteristics for use in damage prevention and risk mitigation in accident scenarios. Example embodiments may include a BiMAC having an inclination of less than 10-degrees from the basemat floor and/or coolant channels of less than 4 inches in diameter, while maintaining minimum safety margins required by the Nuclear Regulatory Commission.
US09368234B2
In a method of operating a nonvolatile memory device, an impedance calibration verifying operation is performed based on a data read command. The impedance calibration verifying operation ascertains whether an impedance calibration operation is normally performed for a data input/output (I/O) terminal of the nonvolatile memory device. A detection value is stored in a storage unit. The detection value indicates a result of the impedance calibration verifying operation. The detection value is output based on a first command received after the nonvolatile memory device receives the data read command. A data read operation or the impedance calibration operation is selectively performed based on the detection value.
US09368231B2
A switched capacitor circuit according to the present invention includes: a capacitor including a first terminal to which the input voltage is applied and a second terminal; a capacitor including a third terminal and a fourth terminal; an inverting amplifier including a second output terminal and a second input terminal which is connected to the fourth terminal; a capacitor including a fifth terminal and a sixth terminal; a capacitor including a seventh terminal and an eighth terminal and included in an electrical path between the second output terminal and the fifth terminal; and a capacitor including a ninth terminal and a tenth terminal connected to the second terminal and the sixth terminal, respectively. The third terminal is connected to the second terminal. The sixth terminal is connected to the output terminal.
US09368229B2
A semiconductor integrated circuit device includes a plurality of column repair address lines configured to cross and a plurality of mat select lines; a fuse set unit including a plurality of latch units electrically coupled with the plurality of column repair address lines and the plurality of mat select lines; a fuse driving unit configured to provide fuse data to the latch units through the plurality of column repair address lines; and an equalizer configured to equalize the fuse data to a same level in response to a select signal of the fuse set unit and a boot-up signal of the fuse set unit.
US09368224B2
To maintain stability of memory array operations, a supplemental current can supply a common source line of a memory array so that the combined current from the memory array and supplemental current is at least a minimum regulation current level. When enabled for sensing operations, a driver circuit maintains the common source line's voltage level. A current subtractor circuit determines the difference between a reference current and a current proportional to the current flowing from the array, where the reference current is proportional to the minimum regulation current. The difference current is then mirrored by a self-adjusting current loop and supplied to the common source line to maintain its current level.
US09368223B2
A memory system includes a nonvolatile memory device including a first memory area formed of memory blocks which store n-bit data per cell and a second memory area formed of memory blocks which store m-bit data per cell, where n and m are different integers, and a memory controller configured to control the nonvolatile memory device. The memory controller is configured to execute a read operation, and to execute a read reclaim operation in which valid data of a target memory block of the second memory area is transferred to one or more memory blocks of the first memory area, the target memory block selected during the read operation. The read reclaim operation is processed as complete when all the valid data of the target memory block is transferred to the one or more memory blocks of the first memory area.
US09368218B2
A flash memory controller is configured to provide a first erase mode for erasing one or more groups of flash memory cells in a flash memory device using a plurality of erase pulses and a second erase mode for erasing the one or more groups of flash memory cells using a single erase pulse. The controller may receive a fast erase signal to erase the one or more groups of flash memory cells and, in response to the signal, switch operating parameters of the flash memory device from first parameters corresponding to the first erase mode to second parameters corresponding to the second erase mode, and instruct the flash memory device to perform an erase operation on the one or more groups of flash memory cells according to the second parameters. The controller may then verify that the erase operation was completed using the single erase pulse.
US09368217B2
A voltage generator includes: a first pump configured to generate and output a first voltage to a first node in response to a first clock signal; a second pump configured to generate and output a second voltage to a second node in response to the first clock signal; a third pump configured to generate and output a third voltage to the first and second nodes in response to the first clock signal; a first switch configured to deliver the third voltage to the first node in response to a first control signal; and a second switch configured to deliver the third voltage to the second node in response to a second control signal, in which the first pump has a first drivability, the second pump has a second drivability, and the third pump has a third drivability greater than the first and second drivabilities.
US09368215B2
A method controls a memory that includes twin memory cells formed in a semiconductor substrate. Each memory cell includes a floating-gate transistor including a state control gate, in series with a select transistor that includes a vertical select control gate, common to the twin memory cells, and a source connected to an embedded source line, common to the memory cells. The drains of the floating-gate transistors of the twin memory cells are connected to a same bit line. The method includes controlling a memory cell so as to turn it on to couple the source line to a bit line coupled to the ground, during a step of programming or reading another memory cell.
US09368213B2
A nonvolatile semiconductor memory device includes a memory cell array having multiple blocks each with a plurality of memory strings. Each memory string has multiple memory cells connected in series between first and second selection transistors. The device further includes a row decoder, a block decoder, first and second signal line groups, and a switch circuit. The row decoder has transfer transistors through which voltages are supplied to the selection transistors. The block decoder supplies a selection signal that indicates whether the first group or the second group has been selected. The first and second signal line groups are connected to the selection transistors of the memory strings that are in the respective first and second memory blocks of the first and second groups. The switch circuit connects the first and second signal line groups to the respective first and second memory blocks of the selected group.
US09368206B1
In one embodiment, a capacitive circuit can include: (i) a resistive storage element having a solid electrolyte, a first electrode coupled to a first side of the solid electrolyte, and a second electrode coupled to a second side of the solid electrolyte; (ii) the resistive storage element being configured to be programmed to a low resistance state by application of a program voltage in a forward bias direction to form a conductive path between the first and second electrodes, and being configured to be erased to a high resistance state by application of an erase voltage in a reverse bias direction to substantially dissolve the conductive path; and (iii) a first capacitor having the first electrode coupled to a first side of a first oxide layer, and a third electrode coupled to a second side of the first oxide layer.
US09368200B2
A low read current architecture for memory. Bit lines of a cross point memory array are allowed to be charged by a selected word line until a minimum voltage differential between a memory state and a reference level is assured.
US09368198B1
A memory device can include a plurality of two terminal conductive bridging random access memory (CBRAM) type memory elements; at least one program transistor configured to enable a program current to flow through at least one memory element in response to the application of a program signal at its control terminal and a program bias voltage to the memory element; and an erase load circuit that includes at least one two-terminal diode-like load element, the erase load circuit configured to enable an erase current to flow through the load element and at least one memory element in a direction opposite to that of the program current.
US09368194B2
A semiconductor integrated circuit which can respond to changes of the amount of retained data at the time of standby is provided. The semiconductor integrated circuit comprises a logic circuit (logic) and plural SRAM modules. The plural SRAM modules perform power control independently of the logic circuit, and an independent power control is performed among the plural SRAM modules. Specifically, one terminal and the other terminal of a potential control circuit of each SRAM module are coupled to a cell array and a local power line, respectively. The local power line of one SRAM module and the local power line of the other SRAM module share a shared local power line. A power switch of one SRAM module and a power switch of the other SRAM module are coupled in common to the shared local power line.
US09368189B2
A semiconductor device includes an output circuit having a plurality of unit buffer circuits, an impedance of each unit buffer circuit of the plurality of unit buffer circuits being adjustable, a control circuit configured to selectively activate one or more unit buffer circuits of the plurality of unit buffer circuits, and an impedance adjustment unit configured to adjust the impedance of each of the unit buffer circuits of the plurality of unit buffer circuits. The impedance adjustment unit includes a first power line, a replica circuit, and a load current generation circuit. The replica circuit and the load current generation circuit are coupled in common to the first power line, the replica circuit has a replica impedance that is substantially equal to the impedance of the output circuit, and the load current generation circuit changes current flowing therethrough.
US09368182B2
Nonvolatile storage with long memory endurance having the advantages of easy manufacturability is obtained by using a memory cell having an information storage element including a ferroelectric material, and operating the memory cell in a volatile operating mode and a nonvolatile operating mode. The option of operating the memory cell in the volatile operating mode enables the associated advantages of high memory speed at long endurance, wherein, however, the option of operating the memory cell in the nonvolatile operating mode can bridge gaps in the power supply.
US09368180B2
In an electronic device including a semiconductor memory, the semiconductor memory may include a unit storage cell including a variable resistor having a resistance value that is changed according to current flowing through both terminals of the variable resistor and a selection element that is electrically coupled to one terminal of the variable resistor, a unit current generation section that generates the current flowing through both terminals by using predetermined voltage according to a polarity of current data as compared with existing data, and a pad that receives the predetermined voltage from an exterior and allows the current flowing through both terminals to be measured from an exterior.
US09368177B2
Provided are a magnetic resistance structure, a method of manufacturing the magnetic resistance structure, and an electronic device including the magnetic resistance structure. The method of manufacturing the magnetic resistance structure includes forming a hexagonal boron nitride layer, forming a graphene layer on the boron nitride layer, forming a first magnetic material layer between the boron nitride layer and the graphene layer according to an intercalation process; and forming a second magnetic material layer on the graphene layer.
US09368175B2
A semiconductor memory device may include: a memory cell array; a first address controller configured to receive a first command and a first address and generate a first control signal in response to the first command; and a second address controller configured to receive a second address and a second command inputted at the same time as the first command, and generate a second control signal in response to the second command.
US09368174B2
A control device that comprises a first data strobe input terminal to be connected in common to data strobe terminals that are included respectively in first memory devices, and a plurality of first sub-units each coupled to the first data strobe input terminal and each holding a data strobe delay value corresponding to an associated one of the first memory devices, and the data strobe delay values of the sub-units being independent from each other.
US09368172B2
A memory controller that extends the window when reading data from the memory device to compensate for fluctuations in a read strobe delay. The memory controller includes a communication port that receives a timing reference signal for reading data from a memory device. A control circuit generates a gating signal indicative of a read window. A gating adjustment circuit generates an adjusted gating signal indicative of an adjusted read window based on the gating signal and the timing reference signal. A gating circuit generates a first gated timing reference signal for reading data by gating a delayed version of the timing reference signal with the adjusted gating signal.
US09368163B2
The present disclosure includes apparatuses and methods for power consumption control. A number of embodiments include determining power consumption information for each phase in a combination of phases of a command, and authorizing execution of at least one of the phases in the combination based, at least partially, on the power consumption information determined for the at least one of the phases.
US09368161B2
A nonvolatile memory (NVM) cell includes a semiconductor substrate having therein an N well and a P well; a first oxide define (OD) region and a second oxide define (OD) region disposed within the N well; a PMOS select transistor disposed on the first OD region; a PMOS floating gate transistor serially connected to the select transistor and being disposed on the on the first OD region, wherein the PMOS floating gate transistor comprises a floating gate overlying the first OD region; and an assistant gate protruding from one distal end of the floating gate to one edge of the second OD region such that the assistant gate is capacitively coupled to the second OD region and the N well. The select transistor, the floating gate transistor and the assistant gate disposed on the same N well.
US09368160B2
According to one embodiment, a memory device includes first to third interconnects, memory cells, and selectors. The first to third interconnects are provided along first to third directions, respectively. The memory cells includes variable resistance layers formed on two side surfaces, facing each other in the first direction, of the third interconnects. The selectors couple the third interconnects with the first interconnects. One of the selectors includes a semiconductor layer provided between associated one of the third interconnects and associated one of the first interconnects, and gates formed on two side surfaces of the semiconductor layer facing each other in the first direction with gate insulating films interposed therebetween.
US09368157B2
A television receiver may detect during a primary recording of particular programming degradation of a received signal quality associated with the particular programming to at or below a predetermined threshold value. The television receiver may instantiate a secondary recording of the particular programming during the primary recording when the particular programming is accessible over at least one terrestrial network. The television receiver may query a computing system to acquire content associated with at least one gap in content within the primary recording present due to received signal quality. The television receiver may output during playback of the primary recording a notification to enable access to the secondary recording when content associated with the at least one gap in content within the primary recording is unavailable over the at least one terrestrial network.
US09368153B2
A disc device records or reproduces information in or from a disc stored in a disc cartridge. The disc cartridge includes a casing having a front face with an opening for receiving the disc; and a cover closing the opening of the casing. The cover includes a slider moving along a side face of the casing, a shutter closing the opening; and a hinge part rotatably coupling the shutter to the slider. The disc device includes a stopper contacting the slider when the disc cartridge is inserted into the disc device to restrict movement of the slider in an insertion direction, and a cam part separating the hinge part from a contact region between the shutter and the casing when or before the casing further moves with the stopper restricting movement of the slider and the shutter is pressed by the casing to rotate about the hinge part.
US09368152B1
Technologies are described herein for performing flexible virtual defect padding of bad sectors on recording media of a storage device. A defective sector on a data track of a recording medium in the storage device is detected. The size and position of a physical defect within the defective sector are determined, and one or more sectors adjacent to the defective sector on the data track are mapped as virtual defects based on the size and position of the physical defect within the defective sector.
US09368146B2
An apparatus comprises a writer, a near-field transducer (NFT), a channel waveguide proximate the NFT, a dielectric layer between the NFT and waveguide, and a plurality of heat sinks. A first heat sink comprises a gap and contacts the NFT and the writer. A second heat sink extends across the gap of the first heat sink and between the NFT and a heat reservoir component, such as a return pole of the writer. The channel waveguide may contact the second heat sink, such as by encompassing a peripheral portion of the second heat sink. The second heat sink may have at least an outer surface comprising a plasmonic material, and may be configured to enhance plasmonic excitation of the NFT.
US09368133B2
A data writer may be configured with at least a write pole and a continuous coil with the continuous coil having a first turn with a first cross-sectional shape and a second turn with a second cross-sectional shape that differs from the first cross-sectional shape. The second turn may be positioned proximal a leading edge of the write pole and an air bearing surface while the first turn is positioned distal the air bearing surface.
US09368119B2
A method for transmitting communications from a vehicle onboard computer system is provided. The method receives a graphical user command via a user interface; converts the user command into a voice instruction; and transmits the voice instruction to an electronic device, using machine-to-machine (M2M) communication.
US09368117B2
Some implementations provide a method for identifying a speaker. The method determines position and orientation of a second device based on data from a first device that is for capturing the position and orientation of the second device. The second device includes several microphones for capturing sound. The second device has movable position and movable orientation. The method assigns an object as a representation of a known user. The object has a moveable position. The method receives a position of the object. The position of the object corresponds to a position of the known user. The method processes the captured sound to identify a sound originating from the direction of the object. The direction of the object is relative to the position and the orientation of the second device. The method identifies the sound originating from the direction of the object as belonging to the known user.
US09368108B2
A speech recognition method and device are disclosed. The method includes: acquiring a text file specified by a user, and extracting a command word from the text file, to obtain a command word list; comparing the command word list with a command word library, to confirm whether the command word list includes a new command word; if the command word list includes the new command word, generating a corresponding new pronunciation dictionary; merging the new language model into a language model library; and receiving speech, and performing speech recognition on the speech according to an acoustic model, a phonation dictionary, and the language model library. Command words acquired online are closely related to online content; therefore, the number of the command words is limited and far less than the number of frequently used words.
US09368085B2
A method and apparatus for driving an active matrix display panel includes a plurality of scanning lines, a plurality of data lies intersecting the scanning lines, and a plurality of pixel electrodes that are coupled to the scanning lines and the data lines. The method includes activating the scanning lines sequentially, and adjusting common voltages applied to a plurality of common electrodes that are disposed opposite to the pixel electrodes in response to differences in voltage changes generated among the pixel electrodes when the scanning lines changes from an on state to an off state. Therefore a voltage difference between each of the pixel electrodes and a common electrode arranged opposite to the pixel electrode is equal to a target voltage.
US09368083B2
A liquid crystal display device includes a liquid crystal display panel; and a driver driving the liquid crystal display panel. The liquid crystal display panel includes: a first substrate on which subpixels each including a pixel electrode are integrated; and a second substrate opposed to the first substrate, a plurality of common electrodes being formed on the second substrate. The display region of the liquid crystal display panel is divided into a plurality of sections respectively corresponding to the common electrodes. When a partial display in which an image is selectively displayed in a selected section is performed, the liquid crystal driver drives the common electrode corresponding to the selected section to a predetermined common voltage level, sets the common electrodes corresponding to the non-selected sections to a predetermined reference level, and sets pixel electrodes of subpixels in the non-selected sections to the reference voltage level.
US09368072B2
Control sections of displays 11 each determine control information Pi used when area-active driving is performed individually and transmit the control information Pi to a multi-display control section 12. The multi-display control section 12 determines control information Ps for the entire device on the basis of the received pieces of control information Pi and transmits the control information Ps to the control sections of the displays 11. All the displays 11 perform area-active driving on the basis of the same control information Ps. In this way, occurrence of a luminance difference or chromaticity difference among display screens of the displays 11 is prevented and the quality of a displayed image is improved.
US09368070B2
A tileable display panel includes an illumination layer, a display layer, and a screen layer. The display layer is disposed between the screen layer and the lamp layer and includes pixelets separated from each other by spacing regions. Each of the pixelets is positioned to be illuminated by lamp light from the illumination layer and to project a magnified image sub-portion onto the backside of the screen layer such that the magnified image sub-portions collectively blend together to form a unified image on the screen layer which covers the spacing regions on the display layer. Each of the pixelets includes core pixels having a common size and a first separation pitch and peripheral pixels surrounding the core pixels on two or more sides which provide a higher image resolution in overlap regions on the screen layer when the magnified image sub-portions overlap on the screen layer.
US09368069B2
A driver includes a first circuit to output a scan signal and a second circuit to output an emission control signal. The first circuit outputs the scan signal based on a first set of clock signals, and the second circuit outputs the emission control signal based on a second set of clock signals. The first set of clock signals and the second set of clock signals have at least one same clock signal and at least one different clock signal. The second circuit receives the scan signal and outputs the emission control signal based on the scan signal. The first circuit may be a scan driver and the second circuit may be an emission control driver of a display device.
US09368066B2
A pixel circuit is disclosed. The pixel circuit includes first and second capacitors, and a driving transistor, which generates a driving current. The pixel circuit includes a first transistor, controlled by a first driving signal, and which transmits a data signal to the first capacitor. The pixel circuit includes a second transistor, controlled by a second driving signal, and which transmits the data signal to the driving transistor. The pixel circuit includes a third transistor, controlled by the first driving signal, and which transmits a reference signal to the driving transistor. The pixel circuit includes a fourth transistor, controlled by a third driving signal, and which transmits the driving current to the light emitting element. The first capacitor stores the data signal and stabilizes the voltage between the gate and the source of the driving transistor, and the second capacitor stabilizes a source voltage of the driving transistor.
US09368058B2
According to one embodiment, a display apparatus includes a plurality of semiconductor layers, a first insulation film, a first conductive layer, a second insulation film and a display element includes a second conductive layer. The first conductive layer and the second conductive layer are opposed to each other to form a capacitance unit.
US09368053B2
Provided is to secure a data-writing period to a source line and reduce the number of the IC chips used. N image data (e.g., three image data, RGB) are sequentially input to one input terminal. Three switches, three first memory elements, three transfer switches, three second memory elements, and three buffers are connected in parallel to the input terminal. The three switches are turned on respectively. RGB image data are held in the three respective first memory elements. In a selection period of a gate line of an (m−1)-th row, image data of an m-th row are written to the first memory elements. When the three transfer switches are turned on in a selection period of a gate line of an m-th row, the image data are transferred to and held in the second memory elements. Then, the image data are output to each source line through each buffer.
US09368049B2
A lever lock is used for attaching first and second support elements in a display structure. The lever lock includes a body that attaches to a side of the first support element. A shaft extends from the body and is oriented to pass through the slot. A foot is disposed at an end of the shaft that is remote from the body and is configured to operatively engage a side of the second support element so as to provide a clamping force on the second support element against the first support element. A lever is coupled to the body and configured to rotate between first and second positions. A linkage connecting the lever with the shaft converts the rotation of the lever into a movement of the shaft through a translation and axial rotation so as to move the foot between engaging and disengaging positions.
US09368047B2
The present invention takes the form of a device for training a user in defibrillation technique. The device includes a non-conductive belt that encircles a chest of a typical training simulator. The device includes conductive studs disposed in the AP or AL position, and therefore allows for training of the AP or AL defibrillation technique, respectively. The device can be used in conjunction with a high-technology simulator. In such a case the conductive studs redirect simulated cardiac rhythm signals and defibrillator electricity, allowing for the simulation of defibrillation in the AP position. The device can also be used in conjunction with a low-technology simulator or a pillow to provide AP and/or AL defibrillation functionality. In such a case, a rhythm simulator is used to simulate heart rhythm and dissipate defibrillation energy.
US09368037B1
A stateful application programming interface training system. The system comprises an interface configured for use in a customer facing production environment, wherein an instance of the interface is launched for each student using the training system; and a training application, wherein the application is configured to receive messages from the instances of the user interface, wherein each message invokes one of a plurality of different application programming interface methods, associate each message to one of a plurality of students, maintain a state of a plurality of training scenarios, a separate state of a training scenario for each of the plurality of students based on an identity of the student, determine when a state of a training scenario completes a checkpoint, and in response to a completed checkpoint, return particularized updated information to the instance of the interface associated with the completed checkpoint.
US09368035B2
A monitoring device including a memory containing a reference path, the memory being separate from a flight management system. The reference path corresponding to a path that is defined during a navigation data validation on ground for the flight management system. A monitoring unit is configured to monitor a current flight path that is determined by the flight management system, by monitoring if this current flight path is in conformity with the reference flight path that is recorded in the memory.
US09368034B2
A rear warning system for a vehicle that detects information regarding an area behind a vehicle and is operated based on the detected information. The system includes sensors configured to detect the information regarding the area behind the vehicle and a guiding device operated by a controller to provide a notification of the information regarding the area behind the vehicle received from the sensors. The sensors include an ultrasonic wave sensor configured to detect a target object spaced farther from the rear of the vehicle than a predetermined distance and a capacitance sensor configured to detect the target object closer than or equal to the predetermined distance.
US09368030B2
Current route information about a traffic situation and/or the state of the route itself is made available. A communication link to a peer-to-peer network is set up by a communication device of a motor vehicle, and the motor vehicle is signed on to said peer-to-peer network as a subscriber of the peer-to-peer network, with the result that a communication address of the motor vehicle can be determined by at least one other subscriber of the peer-to-peer network. Furthermore, in each case an interrogation relating to the route information is received by the communication device from the at least one other subscriber. The route information itself is determined by a sensing device of the motor vehicle and is then transmitted to the interrogating subscriber by the communication device.
US09368010B2
Security printing paper based on a chipless radio frequency (RF) tag and a method of manufacturing the same are provided. The security printing paper based on a chipless RF tag includes first base paper, second base paper, and one or more chipless RF tags. The chipless RF tags are disposed between the first base paper and the second base paper. At least one layer configured to prevent the locations of the chipless RF tags from being exposed to the outside and to enable the security printing paper to be detected is formed on one or more of the first base paper and the second base paper.
US09368008B2
Systems, methods, devices, and computer-readable media detect a status of a cable 204, and in particular, a cable of electric supply equipment. An example of electric supply equipment is electric vehicle supply equipment 200, which may be used for charging an electric vehicle 201. The electric vehicle supply equipment 200 may include a cable 204 for delivering electric power from a power source to the electric vehicle 201. Further, the electric vehicle supply equipment 200 may include a cable detection subcircuit 225 for detecting a status of its cable 204. Specifically, the cable detection subcircuit 225 may detect whether the cable 204 has been removed. Further, the electric vehicle supply equipment 200 may take various actions based on results provided by the cable detection subcircuit 225.
US09368003B2
In an example embodiment, an automated banking machine that operates responsive at least in part to data read from data bearing records. The automated banking machine including a transaction function device, a slot associated with the transaction function device, an indicator adjacent to the slot, the indicator includes at least three different color light emitting diodes (LEDs), and an indicator processor in operative connection with the indicator. The indicator processor is operable to cause the LEDs of the indicator to intermittently illuminate to produce a plurality of blended colors that correspond to a functional status of the transaction function device.
US09367996B2
Various embodiments described herein provide systems and methods for betting contests relating to sports matches and, in particular, relating to fantasy sports associated with sports matches. For some embodiments, the systems and methods described herein establish and conduct one or more betting contests based on the performance of individual real-world sports players. Additionally, for some embodiments, the performance of an individual real-world sports player is determined using fantasy sports points (hereafter, fantasy points) attributed to the individual real-life sports player by one or more fantasy sports systems.
US09367995B2
Examples disclosed herein relate to an electronic gaming device including a memory, a processor, and a plurality of reels. The memory may include one or more turbo boost progressive feature structures. A processor may generate one or more symbols to be located in the one or more areas. The processor may increase a progressive jackpot amount by a first amount where the first amount is a portion of a wager. The processor may increase the progressive jackpot amount by a second amount based on a turbo boost triggering event.
US09367990B2
A system for providing access to casino gaming and sports booking is provided which permits a gambler to place wagers using a location based mobile gaming unit. The gambler may access the system through a wireless network. Further, the gambler may be positioned anywhere there is an established local gaming server. A gambler profile may be provided wireless access to the local server along with the games available in the local server jurisdiction based on a global positioning of the mobile gaming unit.
US09367989B1
A method, device, and system for managing player data includes a player device that communicates with a server. The player device is configured to receive an allocation of game resources stored at the server and/or player device to a game feature in a game conducted, at least in part, using a game device. The game device generates and transmits a stream of game data to the server and/or player device for resolution of the game feature.
US09367985B2
A device for providing an interface to a gaming machine. The device includes a processor, an ID Card reader coupled to the processor, a display coupled to the processor for displaying a bezel and information within the bezel. The device also including a keypad coupled to the processor for receiving input. The processor instructing the display to display media according to a predetermined set of rules.
US09367972B2
Methods and systems are provided for compensating an instantaneous fuel economy reading for stored energy. One method comprises, when a vehicle undergoes a sufficient change in one or more of square of vehicle speed and vehicle altitude, estimating a conversion factor for fuel due to stored vehicle energy and adjusting the instantaneous fuel economy reading by the estimated conversion factor. The adjusted instantaneous fuel economy reading may be displayed to an operator of the vehicle.
US09367971B2
A method for the maintenance of an aircraft including an avionics system including a set of operating units. The avionics system is connected to a ground-based infrastructure via at least one communication medium. Maintenance data stored in the ground-based infrastructure and relating to the malfunction of at least one operating unit are obtained via the at least one communication medium, and at least one operating unit is repaired on the basis of the maintenance data obtained.
US09367969B2
A system for interlocking a vehicle terminal with a portable terminal includes the vehicle terminal configured to correct vehicle data including mileage, self-diagnosis information, and driving information according to an operation. The portable terminal is physically connected with the vehicle terminal and connected with a service server of a control center through wireless communication. The portable terminal is configured to transmit the vehicle data provided from the vehicle terminal to the service server and receive information and a management service provided from the service server. The portable terminal is provided the information and the management service to the vehicle terminal.
US09367965B2
The invention relates to systems and methods for three dimensional imaging of tissue. The invention provides systems and methods to provide a representation of tissue from three-dimensional data in the form of a montage of images having an indication of a spatial registration among the images.
US09367962B2
An augmented image is generated by capturing a visual image of a site with a digital camera, generating a virtual image or associated information from a digital model of the site, and superimposing the virtual image or associated information on the visual image. To register the digital model with the visual image, a sensor pole is introduced into the field of view, and a combined visual image of the site and an optical target on the sensor pole is captured. The position and orientation of the sensor pole with respect to the site reference frame are measured by sensors mounted on the sensor pole; the position and orientation of the digital camera with respect to the sensor pole are calculated from image analysis of the optical target on the sensor pole; and the position and orientation of the digital camera with respect to the site reference frame are calculated.
US09367954B2
Location-mapped environments that provide panoramic and immersive views of street scenes are augmented with modern data visualization displays, to communicate additional information of interest. Specifically, illumination statistics information is mapped onto building facades in the location-mapped environments. The illumination statistics information can include variations of illumination as a function of time of a day and as a function of the season. The illumination statistics information can also include direct illumination statistics information and indirect illumination statistics information. Further, the illumination statistics can be calculated for any window on a building façade to determine natural lighting through that window. The illumination statistics can be employed, for example, to aid users in selection of real estate properties for rental or purchase.
US09367947B2
Remote rendering of three-dimensional images using virtual machines includes using a hypervisor executing on a physical computer to allocate exclusive and direct access to a graphics processing unit in the physical computer, to a first virtual machine. An agent executing on a second virtual machine intercepts three-dimensional draw commands generated by a three-dimensional application and forwards the intercepted draw commands to a rendering agent executing on the first virtual machine. The rendering agent then transmits the intercepted draw commands to the graphics processing unit for rendering upon which the graphics processing unit renders a three-dimensional image from the draw commands. The rendering agent obtains the rendered image from the graphics processing unit and forwards the image to the second virtual machine. Upon receiving the rendered image, the second virtual machine transmits the rendered image to another remote, physical computer where the rendered image is displayed to a user.
US09367945B2
A display control unit included in an object information acquisition apparatus receives information about a depth range, subjected to display of a distribution related to acoustic characteristics, input by a user, and outputs, when the depth range is narrower than a predetermined range, image information for displaying an image of second distribution information subjected to adaptive signal processing in an area corresponding to the depth range or a combined image obtained by combining first distribution information subjected to addition processing with a predetermined weight and the second distribution information.
US09367939B2
A method that receives a visual media item and determines an identity of at least one intended viewer of the visual media item is disclosed. The method may further identify a visual representation of an object that is comprised by the visual media item and determine a relevance of the object based, at least in part, on the identity. The method may further generate a modified visual media item such that the modified visual media item differs from the visual media item, at least, by visual emphasis of the visual representation of the object.
US09367929B2
Systems and methods for monitoring Web page content associated with processing a resource request are provided. A client computing device generates a sample image corresponding to a set of resources rendered in response to a resource request. A processing component, such as an image analysis component, then compares the sample image with an averaged reference image to identify a compared image. The averaged reference image is determined from averaging a pixel intensity value for each pixel in a first reference image with a pixel intensity value for each pixel in a second reference image. These first and second reference images both correspond to the same set of requested resources. The processing component then weights the compared image to produce a weighted compared image and determines whether a sum of the intensity values for each pixel in the weighted compared image exceeds a threshold. Aspects of systems and methods for generating an alert message if the threshold is exceeded are also provided.
US09367927B2
The moving image region detection device includes an updated block detection means, a natural image updated block determination means, and a moving image block extraction means. The updated block detection means compares pixel values between a frame of an input video and the previous frame, and detects a block including a pixel in which a value having been changed, as an updated block. The natural image updated block determination means calculates an index value representing a degree of continuity of changes in pixel values in the updated block, compares the calculated index value with a threshold, and determines whether it is an updated block of a natural image. The moving image block extraction means extracts a block determined to be an updated block of a natural image a given number of times or more in most recent frames including the frame, as a moving image block of a natural image.
US09367924B2
A method and system for fully automatic liver segmentation in a multi-channel magnetic resonance (MR) image is disclosed. An initial liver boundary in the multi-channel MR image, such as an MR Dixon scan. The segmented initial liver boundary in the multi-channel MR image is refined based on features extracted from multiple channels of the multi-channel MR image using a trained boundary detector. The features may be extracted from an opposed channel and a water channel of an MR Dixon scan.
US09367918B2
A multi-view stereo approach generates an inventory of objects located on an object holder. An object may be a sample tube and an object holder may be a tube rack as used in lab automation for healthcare diagnostics. A processor performs 3D tracking of the object holder and the geometric analysis of multiple images generated by a calibrated camera. A homography mapping between images is utilized to warp a second image to a viewpoint of a first image. Plane induced parallax causes a normalized cross-correlation score between the first image and the warped second image of a location on the holder that has an object that is significantly different from a normalized cross-correlation score of a location that has not an object and enables the processor to infer tube inventory and absence or presence of a tube at a location in a rack.
US09367916B1
A system, article, and method of run-time self-calibrating lens shading correction.
US09367915B2
A method of analyzing an OCT image. An OCT image has many differently colored dots. The system detects the number of differently colored dots, quantifies them and performs statistical analyses to determine a likelihood of disease. The different colored dots correspond to different retina cell types and structures.
US09367913B2
A system (100) for segmenting an object in an image adapts a first model for segmenting the object to the image. A feature is extracted from the image based on the adapted first model. A second model is selected for segmenting the object from a plurality of models for segmenting the object, based on the feature extracted from the image. The second model includes additional detail of the object. The second model is utilized based on the adapted first model and/or the feature extracted from the image; the initialized second model is adapted to the image. The features extracted from the image based on the adapted first model help the system (100) to select the second model for segmenting the object from a plurality of models for segmenting the object. The adapted first model and/or the extracted features are also used for initializing the second model. Because the second model includes the additional detail of the object, the segmentation result using the second model is more complete than the segmentation result Obtained using the first model. Moreover, the initialization of the second model based on the adapted first model and/or the detected features Improves the accuracy of the second model adaptation.
US09367903B2
Artifacts caused by scattered radiation when generating X-ray images of objects are corrected using a temporally alterable modulation of the primary radiation. A respective set of originally amplitude-modulated modulation projections of the object is generated and a respective scattered image allocated to the respective modulation projections is calculated. The method is particularly suitable for fast CT scans.
US09367902B2
An image processing device includes an isolated point noise detection section, and an isolated point noise correction section. The isolated point noise detection section determines whether or not isolated point noise is included within a given area based on a first index value that represents the range of first to nth pixel values being obtained by arranging the pixel values of pixels within the given area including an attention pixel in ascending or descending order, and a second index value that represents the range of a pixel value group being obtained by excluding at least one of the first pixel value and the nth pixel value from the first to nth pixel values. The isolated point noise detection section determines whether or not the attention pixel is a pixel that corresponds to isolated point noise when it has been determined that isolated point noise is included within the given area.
US09367891B2
Methods, systems and non-transitory computer readable media are described. A system includes a shader pipe array, a redundant shader pipe array, a sequencer and a redundant shader switch. The shader pipe array includes multiple shader pipes, each of which perform rendering calculations on data provided thereto. The redundant shader pipe array also performs rendering calculations on data provided thereto. The sequencer identifies at least one defective shader pipe in the shader pipe array, and, in response, generates a signal. The redundant shader switch receives the generated signal, and, in response, transfers the data destined for each shader pipe identified as being defective independently to the redundant shader pipe array.
US09367883B2
Various embodiments relating to synchronizing changes to a shared list of items between different devices are provided. In one embodiment, a first set of change operations for a first version of a shared list may be received from a first device. The first set of change operations may be performed on the first version of the shared list to produce a second version of the shared list. A second set of change operations for the first version of the shared list may be received from a second device. The second set of change operations may be performed on the second version of the shared list to produce a third version of the shared list that maintains changes that are made by the first set of change operations but that are not made by the second set of change operations.
US09367882B2
A waferstart process for integrated circuit fabrication includes entering order information from requested wafers into a computer through a data input interface of the computer. A container is provided including supplied wafers and having a machine-readable medium associated therewith. The machine-readable medium is encoded with wafer data pertaining to the supplied wafers. The wafer data is entered from the machine-readable medium associated with the container into the computer. The order information and the wafer data are compared within the computer to create a verified data set in the computer upon the computer determining that the supplied wafers in the container correspond to the requested wafers in the order information. The verified data set is stored in a storage medium within the computer. The supplied wafers are transferred from the container to a front opening unified pod after creating the verified data set.
US09367876B2
A system is disclosed for multimedia multipoint real-time conferencing that includes a communication module to receive a request to share media content in a virtual room setting. The content may include an audio, a video, a text, or a HyperText Markup Language (HTML) code referencing a third-party resource. The system may further include a content encoder at the host website to create a data packet encapsulating the transport characteristics and the routing requirements and a multipoint router to share the content via the transport protocol in the real-time group conference associated with the users of the virtual room.
US09367872B1
Embodiments of the present disclosure relate to a data analysis system that may automatically generate memory-efficient clustered data structures, automatically analyze those clustered data structures, automatically tag and group those clustered data structures, and provide results of the automated analysis and grouping in an optimized way to an analyst. The automated analysis of the clustered data structures (also referred to herein as data clusters) may include an automated application of various criteria or rules so as to generate a tiled display of the groups of related data clusters such that the analyst may quickly and efficiently evaluate the groups of data clusters. In particular, the groups of data clusters may be dynamically re-grouped and/or filtered in an interactive user interface so as to enable an analyst to quickly navigate among information associated with various groups of data clusters and efficiently evaluate those data clusters in the context of, for example, a fraud investigation.
US09367871B2
A system, method, and computer-readable storage medium configured to anticipate travel by payment account holders without using payment transaction data.
US09367867B2
A system and method for provisioning Internet access services to guests of a facility (e.g., one or more hotel chains). Equipment and devices for access service are installed throughout the facility. Each device that supports the Internet access services has a unique identifier. Zones representing various public and private areas within each facility are defined and one or more devices are associated with each zone. Service offerings for wired and wireless connections are defined and associated with one or more zones. Service offerings are also paired with pricing plans that provide various payment options and amounts. A web-based administration application allows an administrator to define and manage service offerings associated with the zones. The application also allows the administrator to define and manage the pricing plans. The ability to customize offerings in each facility allows development of consistent offerings, regardless of the size or layout of the facility.
US09367860B2
A system and method for generating and implementing a barcode is provided, wherein the system includes a data generation device configured to receive data and generate barcode data response to the received data, a barcode generation device, configured to receive the barcode data and generate a barcode responsive to the received barcode data, a display device, configured to display the barcode and a barcode receiving device, configured to receive the barcode and operate in response to the barcode.
US09367845B2
A bank customer's CE device is texted by a bank computer when the customer's electronic debit or credit card (“e-card”) is sought to be used so that the customer is alerted to possibly fraudulent “fishing” of the e-card data by a nearby thief device.
US09367836B2
Embodiments of the invention are directed to systems, methods, and computer program products for processing and tracking merchant deposits. An exemplary apparatus is configured to receive a deposit package that contains one or more deposit items which have been placed in the deposit package by a merchant. The deposit package may also contain and/or be coupled with visual indicia that has been created by the merchant. The visual indicia may specify information about the one or more deposit items placed in the deposit package. The apparatus may be further configured to read the visual indicia upon receiving the deposit package and track the deposit package based at least partially on the visual indicia.
US09367832B2
For providing synchronization of image data among diverse devices and applications, exemplary systems include a direct client application providing a user interface operable to allow a user to organize image data according to albums, and to select one or more albums for synchronization with one or more server interfaces that provide various image data manipulation, sharing, and features related thereto. Systems also include an intermediary system to assist in synchronization of select albums with handheld devices, and a notification server to provide scalable notifications of album updates made at server interfaces by users. Exemplary methods include steps providing for selection, from direct client applications, of albums to synchronize with devices, including handheld devices, and various steps of providing updates and notifications among appropriate system components.
US09367830B2
Various embodiments are directed to a method for fulfilling orders from an inventory comprising serialized products. For example, a computer system may receive an order and derive from the order a plurality of products, a unit quantity for each of the plurality of products, and a serial identifier referencing a first product unit of at least one of the plurality of products. At least one of the plurality of products may be a non-reserved product. Also, the computer system may determine a first bin selected from a plurality of non-reserved product bins that is associated with product units of the non-reserved product and generate a pick instruction specifying the first bin and the unit quantity of the non-reserved product specified by the order. The computer system may also instruct a robot to retrieve the first product unit from one of the plurality of robot accessible bins. The robot may be programmed to load product units to the plurality of robot-accessible bins and retrieve product units from the plurality of robot-acccessible bins.
US09367827B1
Disclosed herein is a cross-dock management system comprises: a plurality of movable platforms configured to hold one or more pallets or parcels; at least one barcode or RFID tag positioned on each of said movable platforms, pallets, or parcels, wherein the barcode readers are configured to read the barcodes and RFID readers are configured to read the RFID tags. The data scanned by the barcode readers and RFID readers is stored in a local warehouse database and is used to determine an optimized placement and load for each movable platform in the warehouse.
US09367813B2
Methods and systems for scalable extraction of episode rules using incremental episode tree construction in a multi-application event space comprise compiling events from multiple, different domain logs into in a universal log file, rolling domain-dependent and domain-independent windows through the universal log file to identify distinct event-pattern episodes, adding episodes to an episode tree data structure, pruning less frequent episodes from the episode tree, analyzing the episode tree to identify frequent episode rules, and applying the frequent episode rules to future interactions with users.
US09367812B2
Methods and systems for determining the selection criteria that in its embodiments can distinguish compounds that successfully meet an objective from those that do not, determine the importance of selection criterion in selecting test compounds that have a high probability of achieving an objective and automatically apply the selection criteria to select test compounds with a high chance of meeting an objective.
US09367809B2
Contextual graph matching based anomaly detection may include evaluating computer-generated log file data to create a master directed graph that specifies known events and transitions between the known events. The master directed graph may be processed to determine a plurality of decomposed master graph walks. Incoming computer-generated log file data may be evaluated to create an incoming directed graph that specifies unknown events and transitions between the unknown events. The incoming directed graph may be processed to determine a decomposed incoming walk. Overlap, distance difference, and correlation scores may be determined for each walk pair of a plurality of walk pairs including each of the plurality of decomposed master graph walks and the decomposed incoming walk. One of the decomposed master graph walks may be selected based on the overlap score, the difference score, and the correlation score, to detect an anomaly.
US09367802B2
Techniques are described for determining what node of a classification and regression tree (CART) should be used by a predictive analysis application. A first approach is to use a standard deviation of the data at a given the level of the CART to determine whether data in the next, lower node is more consistent than the data in the current node. A second approach is to measure a correlation between data points in a given node and the time at which each point was sampled (or other correlation metric) to identify a preferred node.
US09367788B2
Arrangement for connecting set values concerning performance relating to an electronics device to the electronics device, more particularly to a power electronics device, such as a frequency converter, which arrangement includes a rating plate part. The rating plate part is a separate unit belonging to the nameplate arrangement of the electronics device, which unit may be affixed to the electronics device. The rating plate part includes a memory member, in which values concerning the performance of the device are recorded. The rating plate part further includes an area in which information corresponding to the information recorded in the memory member is printed and which area remains visible when the rating plate part is affixed to the electronics device.
US09367781B2
A method and a system for encoding and decoding a mobile phone based two-dimensional code are provided, by means of obtaining the data information inputted by a user and transforming the data information into a two-dimensional code the encoding of the two-dimensional code is embodied. Furthermore, by means of performing binarization processing on the two-dimensional code image to obtain the binary data information, which is parsed into text information by using the preset decoding algorithm, to facilitate mobile phone users in information exchanging using a two-dimensional code.
US09367773B2
A system for printing a document that includes one or more target fonts that are emulated with at least one substitute font in a manner that preserves the original pagination and line breaks of the document. A table is provided that lists strategies/logic for enabling the printing device to emulate each of a plurality of predetermined target fonts with a substitute font. These emulation strategies may include but are not limited to, identifying at least one of a resident font for the printing device, stretchable font, local font, downloadable font, font data provided by a 3rd party, or font data that is embedded in a received document. Target font metrics may be employed as “hints” to refine emulation information for the target font data.
US09367771B2
An apparatus includes an acquisition unit configured to acquire a plurality of pieces of information from a medium, a deletion unit configured to delete a second oldest piece of information, which is next to an oldest piece of information, from the plurality of pieces of information acquired by the acquisition unit, an addition unit configured to add new information to the plurality of pieces of information from which the second oldest piece of information has been deleted by the deletion unit, and a printing unit configured to print on a new medium the plurality of pieces of information resulting from the addition by the addition unit.
US09367767B2
Provided is a data processor for generating three-dimensional image data from two-dimensional original image data, the three-dimensional image data including depth value, the apparatus comprising: a first clustering processor for dividing the two-dimensional original image data into a first plurality of clusters based on brightness; a three-dimensional data generating unit for setting a predetermined direction as a brighter-to-darker direction, and for generating information, as first depth information, such that depth value for a first cluster among the plurality of clusters is set to be larger than depth value for a second cluster which neighbors the first cluster and is located nearer to a starting point of the brighter-to-darker direction than the first cluster where the brightness of the first cluster is darker than the brightness of the second cluster.
US09367765B2
In one or more embodiments described herein, there is provided a method of training an apparatus. The method trains the apparatus to automatically detect features of interest in an image. An image is received, the image being of at least one object for inspection, each image comprising a plurality of pixels. The image is segmented into a plurality of superpixels, each superpixel comprising a plurality of pixels which each have similar image data attributes to one another. The superpixels are classified into at least two classes in response to user input identifying at least one feature of interest in one or more of the super-pixels. From a library of image data attributes, a subset of image data attributes is determined that provides preferential discrimination between the at least two classes. The apparatus is then trained using said determined subset of image data attributes to thereby enable the apparatus to classify super-pixels of an image into the at least two classes.
US09367751B2
This object detection device for the area around a vehicle is provided with an imaging device and an image processing device. The image processing device is configured from a detection area setting unit, three area processing units, and an integration processing unit. The detection area setting unit sets a trio of small, medium, and large detection areas within a one-frame image captured by the imaging device. Detection processing for the presence of objects within the trio of small, medium, and large detection areas is carried out for each detection area simultaneously and in parallel by the three area processing units using pattern matching. The integration processing unit integrates the plurality of detection results resulting from detection processing by the plurality of area processing units and outputs the result. As a result, the present invention makes it possible to reduce the amount of time required for detection processing.
US09367749B2
An object detection apparatus mounted in a vehicle for detecting a target object in various changing environmental conditions. In the apparatus, a storage prestores plural image recognition dictionaries each describing reference data for the target object, and plural image recognition techniques each used to detect the target object from an input image with use of one of the plural image recognition dictionaries. A first acquirer acquires an operating state of a lighting device of the vehicle. A selector selects, according to the acquired operating state of the lighting device, one of the plural of image recognition dictionaries and one of the plural of image recognition techniques. A detector detects the target object in the input image by applying image recognition processing thereto with use of the selected image recognition dictionary and technique.
US09367742B2
An object monitoring apparatus includes: an image receiver to receive at least one frame of captured images; an edge image generator to generate an edge image by detecting edges of objects appearing in the frame; a reference image generator to generate a reference image by detecting a part corresponding to a background in the frame to thereby define the detected part as a background edge; a candidate object extractor to extract one or more candidate object pixels by comparing the edge image with the reference image, and to extract a candidate object by grouping the extracted candidate object pixels into the candidate object; and an object-of-interest determiner to determine whether the candidate object is an object-of-interest based on a size of the candidate object and a duration time of detection of the candidate object.
US09367738B2
Apparatus for calculating current distribution inside brain includes: initial grid setting unit configured to set grid points constituting grid with predetermined pitch; current calculating unit configured to calculate current value at each grid point based on the electromagnetic information, by solving forward problem to obtain lead field matrix and by solving inverse problem to obtain current source vector; sub-grid setting unit configured to set grid points constituting sub-grid with smaller pitch, only for subset of the previously set grid, based on the current value at each grid point calculated in the preceding current calculating step; and calculation executing unit configured to repeat setting the sub-grid and calculating the current source vector by the sub-grid setting unit and the current calculating unit one or more times, after calculation of current source vector corresponding to the initial grid is executed by the initial grid setting unit and the current calculating unit.
US09367735B2
In an object identification device, each score calculator extracts a feature quantity from the image, and calculates a score using the extracted feature quantity and a model of the specified object. The score represents a reliability that the specified object is displayed in the image. A score-vector generator generates a score vector having the scores as elements thereof. A cluster determiner determines, based on previously determined clusters in which the score vector is classifiable, one of the clusters to which the score vector belongs as a target cluster. An object identifier identifies whether the specified object is displayed in the image based on one of the identification conditions. The one of the identification conditions is previously determined for the target cluster determined by the cluster determiner.
US09367733B2
Surveillance systems may be found in both private and public spaces. In private spaces, they can be designed to help provide and monitor secure premises. Similarly, public spaces may also use surveillance systems to determine an allocation of public resources. A camera surveillance system according to an embodiment of the invention uses advanced image processing techniques to determine whether an object moving across a scene is a person. The camera surveillance system achieves an accurate and efficient classification by selectively processing a set of features associated with the object, such as features that define an omega shape. By selectively processing the set of features associated with the object, the methods and systems described herein reduce the computational complexity of standard image processing/object detection techniques.
US09367726B1
A barcode reader may perform image processing functions to generate distinct image data records from the frame of image data of a barcode, select an image data record from the distinct image data records and decode the selected image data record. Each image data record may be generated by applying a distinct image processing function to the frame of image data. The barcode reader may capture multiple frames of image data in sequence based on image capture parameters. At least one of the multiple frames of image data may be captured with a distinct parameter value. The image capture parameters may include an exposure setting, a gain setting, a resolution setting, and/or an illumination setting.
US09367725B2
A method and apparatus for decoding codes applied to objects for use with an image sensor that includes a two dimensional field of view (FOV), the method comprising the steps of providing a processor programmed to perform the steps of obtaining an image of the FOV and applying different decode algorithms to code candidates in the obtained image to attempt to decode the code candidates wherein the decode algorithm applied to each candidate is a function of the location of the code candidate in the FOV.
US09367715B2
A system for identifying identity (ID) and an ID card using the same are provided in the present invention. The ID card utilizes a specific ID reader to identify the ID of the ID card. The ID card includes a card case, a plurality of disposing positions for electrodes and at least a specific conductor electrode. The disposing positions are disposed in the card case. The specific conductor electrode(s) is/are disposed on at least one of the disposing positions according to the ID of the ED card. The specific card reader includes a flat panel sensor. When the ID card is close to the flat panel sensor of the card reader, the flat panel sensor senses the position of the conductor electrode(s) to determine the ID of the ID card.
US09367711B1
Embodiments of the present invention provide RFID systems having battery-assisted, Semi-Passive RFID tags that operate with sensitive transistor based square law tag receivers utilizing a plurality of tag receiver dynamic range states. Embodiments of the present invention are also enhanced with receiver training and synchronizing methods suited to the high tag sensitivity and need for dynamic range state switching. These enhancements may employ pseudo-random sequence based receiver training, activation signaling, and frame synchronizing. Further enhancement is achieved via design of system command sets and tag state machine behavior that control system interference and allow maximum usage of high sensitivity. Command set design also allows for convenient expansion to active transmitters and receivers in tags operating within the same system. Additional enhancement attained via power leveling methods that optimize the amount of transmitted power and interference from a reader in relation to the sensitivity of the RFID tags, their ranges from the reader, and the unique physics of the backscatter RFID radio link.
US09367706B2
Access to some aspect of a service may be limited until a user has invested in performing some amount of computation. Legitimate users typically have excess cycles on their machines, which can be used to perform computation at little or no cost to the user. By contrast, computation is expensive for for-profit internet abusers (e.g., spammers). These abusers typically use all of their computing resources to run “bots” that carry out their schemes, so computation increases the abuser's cost by forcing him or her to acquire new computing resources or to rent computer time. Thus, the providers of free services (e.g., web mail services, blogging sites, etc.), can allow newly registered users to use some limited form of the service upon registration. However, in order to make more extensive use of the service, the user can be asked to prove his legitimacy by investing in some amount of computation.
US09367699B2
Embodiments of the present invention provide for a method, system, and apparatus for creating a publishable computer file. The method includes selecting a first computer file encapsulating a source security policy for a computing device and creating a second computer file using the source security policy of the first computer file to create a local security policy and to encapsulate the created local security policy and also an operating system security policy. The method further includes calculating a hash value for the second computer file and storing the hash value in a header for the second computer file. The method yet further includes encrypting the second computer file, wherein the encrypted second computer file once loaded into memory of the computing device is processed by the computing device.
US09367698B2
A communication apparatus performs encryption on data transmitted from another communication apparatus by using first or second cryptographic algorithm, or performs decryption on the data that has been encrypted using the first or second cryptographic algorithm, by using one of the first and second cryptographic algorithms used for the encryption, where the second cryptographic algorithm provides a higher security level than the first cryptographic algorithm. The communication apparatus includes an encryption unit configured to perform, upon receiving the data including a cryptographic class identifying a parameter to be used for performing the encryption or the decryption, the encryption or the decryption by using one of the first and second cryptographic algorithms, based on the cryptographic class.
US09367689B2
An apparatus including a BIOS read only memory (ROM) and a tamper detector. The BIOS ROM includes BIOS contents stored as plaintext, and an encrypted message digest comprising an encrypted version of a first message digest that corresponds to the BIOS contents. The tamper detector is coupled to the BIOS ROM, and accesses the BIOS contents and the encrypted message digest upon reset of a microprocessor, and directs the microprocessor to generate a second message digest corresponding to the BIOS contents and a decrypted message digest corresponding to the encrypted message digest using the same algorithms and key that were employed to generate the first message digest and the encrypted message digest, and compares the second message digest with the decrypted message digest, and precludes the operation of the microprocessor if the second message digest and the decrypted message digest are not equal.
US09367685B2
A device may identify a set of features associated with the unknown object. The device may determine, based on inputting the set of features into a threat prediction model associated with a set of security functions, a set of predicted threat scores. The device may determine, based on the set of predicted threat scores, a set of predicted utility values. The device may determine a set of costs corresponding to the set of security functions. The device may determine a set of predicted efficiencies, associated with the set of security functions, based on the set of predicted utility values and the set of costs. The device may identify, based on the set of predicted efficiencies, a particular security function, and may cause the particular security function to be executed on the unknown object. The device may determine whether another security function is to be executed on the unknown object.
US09367683B2
Systems and methods that use probabilistic grammatical inference and statistical data analysis techniques to characterize the behavior of systems in terms of a low dimensional set of summary variables and, on the basis of these models, detect anomalous behaviors are disclosed. The disclosed information-theoretic system and method exploit the properties of information to deduce a structure for information flow and management. The properties of information can provide a fundamental basis for the decomposition of systems and hence a structure for the transmission and combination of observations at the desired levels of resolution (e.g., component, subsystem, system).
US09367666B2
Methods, systems, and apparatus, including medium-encoded computer program products, for mapping cognitive to functional ability include receiving data regarding assessments of a cognitive ability and assessments of a functional ability; processing the received data to generate a map of one or more cognitive processes underlying the cognitive ability to a continuous-valued measure of the functional ability; and storing the generated map on a computer-storage medium to be used by a computer device in continuous-valued assessments of the functional ability.
US09367664B2
A mobile apparatus includes a sensing handler and a processing handler. The sensing handler includes a plurality of sensing operators. The sensing operator senses data during a sensing time corresponding to a size of C-FRAME and stops sensing during a skip time. The C-FRAME is a sequence of the sensed data to produce a context monitoring result. The processing handler includes a plurality of processing operators. The processing operator executes the sensed data of the sensing operator in a unit of F-FRAME. The F-FRAME is a sequence of the sensed data to execute a feature extraction operation.
US09367658B2
Embodiments of the invention provide a method and apparatus for generating programmable logic for a hardware accelerator, the method comprising: generating a graph of nodes representing the programmable logic to be implemented in hardware; identifying nodes within the graph that affect external flow control of the programmable logic; retaining the identified nodes and removing or replacing all nodes which do not affect external flow control of the programmable logic in a modified graph; and simulating the modified graph or building a corresponding circuit of the retained nodes.
US09367655B2
The present disclosure provides a method. The method includes obtaining an integrated circuit (IC) layout. The method includes providing a polishing process simulation model. The method includes performing a lithography pattern check (LPC) process to the IC layout. The LPC process is performed at least in part using the polishing process simulation model. The method includes detecting, in response to the LPC process, possible problem areas on the IC layout. The method includes modifying the polishing process simulation model. The method includes repeating the performing the LPC process and the detecting the possible problem areas using the modified polishing process simulation model.
US09367643B2
Disclosed are systems, apparatus, methods, and computer readable media for suppressing network feed activities using an information feed in an on-demand database service environment. In one embodiment, a message is received, including data indicative of a user action. An entity associated with the user action is identified, where the entity is a type of record stored in a database. A type of the entity is identified. It is determined whether the entity type is a prohibited entity type. When the entity type is not a prohibited entity type, the message data is saved to one or more tables in the database. The tables are configured to store feed items of an information feed capable of being displayed on a device. When the entity type is a prohibited entity type, the saving of the message data, to the one or more tables in the database configured to store the feed items, is prohibited.
US09367632B2
Requests (94) for location-dependant information, received from a mobile device (1) having a location-finding capability (10), are processed by middleware (4, 40) which identifies the handset type and generates instructions (93, 95) specific to the handset type to provide the data (94, 97) required to generate the required data (99) in a format compatible with the handset (1).
US09367624B2
In one embodiment, an indication of a request pertaining to a user account is obtained, where the user account is associated with at least one user. An account type of the user account is determined, where the account type is one of two or more account types. One or more actions indicated by the request are performed based, at least in part, upon the account type.
US09367620B2
A method, system, and/or computer program product handles a query generated by a user of one of multiple local network devices that are coupled to a network. Multiple system queries are autonomously issued, by a computer that is coupled to the network, requesting states of the local network devices. Query statements, responsive to the system queries and being sent to a wide area network search engine, are intercepted. A natural language query, which is a logical query that is answered by one of the multiple query statements, is generated from one of the multiple query statements. An unstructured query, from a user, about a state of a particular device is received. The unstructured query from the user is compared with the natural language query in order to determine if a match between the query from the user with the natural language query exceeds a predetermined threshold value.
US09367618B2
Embodiments are directed towards managing mobile searches by enabling a user to indicate a context of a search query to narrow a scope of the search. A user may fine tune a search by selecting from a plurality of pre-defined contexts for which to perform a search query. In one embodiment, the user may combine two or more pre-defined contexts to create more complex contexts for use in customized context search queries. The user also enters one or more search terms. A subset of databases is selected from a plurality of databases associated with different subject categories. The subset of databases is selected as predefined by an operator based on the user's context, and searched based on the user's entered search terms and selected context. Results are then aggregated and provided to the user. Results may be rank ordered based on the given user context or user's previous search behavior.
US09367616B2
The video descriptor generation device includes a first extraction unit, a second extraction unit, and a feature combining unit. The first extraction unit extracts a first feature for each picture which is a frame or a field of a video. The second extraction unit extracts a second feature from a region defined by an edge of an image included in the video. The feature combining unit combines the first feature and the second feature to generate a video descriptor.
US09367615B2
Systems and methods are disclosed for displaying available or recommended electronic multimedia content to a user, including electronic media content on the Internet. According to one implementation, a method is provided that includes receiving a request from a user, the request specifying electronic media content desired by the user; analyzing an indexed web history of a plurality of other users, based on the request for desired content; and selecting and sorting a subset of available content groups, based on the request for desired content and the indexed web history. The method also includes selecting and sorting, for each selected and sorted content group, a subset of available content; providing instructions to display, to a user, the selected and sorted content groups along a first axis of a two-dimensional grid; and further providing instructions to display, to the user, the selected available content for each content group along a second axis of the two-dimensional grid.
US09367612B1
A system identifies a set of initial segments of a time-based data item, such as audio. The segments can be defined at regular time intervals within the time-based data item. The initial segments are short segments. The system computes a short-timescale vectorial representation for each initial segment and compares the short-timescale vectorial representation for each initial segment with other short-timescale vectorial representations of the segments in a time duration within the time-based data item (e.g., audio) immediately preceding or immediately following the initial segment. The system generates a representation of long-timescale information for the time-based data item based on a comparison of the short-timescale vectorial representations of the initial segments and the short-timescale vectorial representations of immediate segments. The representation of long-timescale information identifies an underlying repetition structure of the time-based data item, such as rhythm or phrasing in an audio item.
US09367606B1
The present invention is directed to methods of and systems for ranking results returned by a search engine. A method in accordance with the invention comprises determining a formula having variables and parameters, wherein the formula is for computing a relevance score for a document and a search query; and ranking the document based on the relevance score. Preferably, determining the formula comprises tuning the parameters based on user input. Preferably, the parameters are determined using a machine learning technique, such as one that includes a form of statistical classification.
US09367605B2
The present disclosure provides an information search method and system applicable in an information search system wherein each document has corresponding forward index data to address the issue of low search efficiency suffered by existing information search techniques. In one aspect, the method may include: receiving an inquiry word and obtaining one or more keywords contained in the inquiry word by segmentation; searching one or more documents matching the one or more keywords and forward index data corresponding to the one or more documents through the information search system's inverted index data; and determining an abstract of each of the one or more documents according to a corresponding document's forward index data, and outputting the abstract and information of the one or more documents as a search result. The proposed techniques can increase efficiency of information search and, at the meantime, guarantee accuracy of the search to a certain extent.
US09367587B2
Systems, methods, and computer readable storage mediums are provided for selecting a media content object for a user using a combination of inputs. A media input seed associated with a user is obtained. A plurality of channels of media content objects is obtained. At least one of the plurality of channels is associated with the media input seed. Also, in some embodiments, each media content object of each of those channels has a score specific to that channel. A combination score for a respective media content object is calculated based at least in part on that respective media content object's channel specific score for each of at least two of the plurality of channels. Then at least some of the media content objects are ranked based at least in part on their respective combination scores. Finally, at least one ranked media content object is then selected for transmission.
US09367579B1
Various methods and systems for implementing a file change log in a distributed file system are disclosed. In one embodiment, a method involves operating a distributed file system that presents a namespace and maintaining a file change log for the namespace. Operating the distributed file system involves executing an instance of a file system on each of several nodes. Maintaining the file change log can involve maintaining a single file change log for the namespace. Updates to the single file change log can be handled by a primary node or controlled using a locking mechanism. Alternatively, several private file change logs (e.g., one per node) can be maintained, and these private file change logs can be merged into a single file change log (e.g., by a primary node).
US09367575B1
The present disclosure provides for a fingerprint service that maintains a fingerprint index configured to support a number of dissimilar fingerprint types. In one embodiment, the fingerprint service receives a lookup request, where the lookup request comprises one or more fingerprint descriptors, and each of the one or more fingerprint descriptors comprises a fingerprint value and a corresponding fingerprint type. A first fingerprint descriptor of the one or more fingerprint descriptors is identified. A first sub-index of a fingerprint index is selected, where the first sub-index is associated with a first fingerprint type of the first fingerprint descriptor. A lookup operation for a first fingerprint value of the first fingerprint descriptor is performed in the first sub-index. In response to the first fingerprint value being present in the first sub-index, information associated with the first fingerprint value is returned.