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公开(公告)号：US20240356561A1
公开(公告)日：2024-10-24
申请号：US18762215
申请日：2024-07-02
发明人： Nicola Lupo , Enrico Mammei , Michele Bartolini , Stefano Colli
摘要： A method to drive a digital to analog converter (DAC), the method including setting a reference current for the DAC with a reference current source, a base voltage being responsive to changes in a reference voltage at a reference node coupled with the reference current source; sensing a change in the reference voltage; and adaptively steadying the base voltage based on the change in the reference voltage to maintain proportionality between an output current of the DAC and the reference current.
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2.发明公开公开(公告)号：US20240355495A1
公开(公告)日：2024-10-24
申请号：US18300203
申请日：2023-04-13
发明人： Jens Repp
摘要： A device includes a plurality of digital-to-analog converters (DACs), a multiplexer, a plurality of electrodes including a first electrode, and a plurality of direct current (DC) offset circuits including a first DC offset circuit. At least one of the plurality of electrodes is located along a lane for movement of an ion. The multiplexer has multiple inputs coupled to the plurality of DACs and multiple outputs including a first output. The first output is configured to provide a first voltage. The first DC offset circuit is coupled between the first output and the first electrode. The first DC offset circuit is configured to add a first DC offset voltage to either the first voltage or the first voltage amplified by a first gain. The first DC offset voltage is configurable.
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公开(公告)号：US12126955B1
公开(公告)日：2024-10-22
申请号：US17965402
申请日：2022-10-13
CPC分类号： H04R1/1066 , H03M1/66 , H04R5/033 , H04R5/04
摘要： A cabin management system is described. The cabin management system includes a housing. The housing is configured to receive one or more modules. The modules may be detached and reattached to the housing. The modules may be rearranged to achieve a desired layout of touchscreens, audio converter, and input/output ports. The modules may include a geometry which provides a flush-mounting between the housing and the modules. The flush-mounting may prevent a passenger from accessing the cavity defined by the housing. The audio converter includes a digital-to-analog converter and an audio jack. The digital-to-analog converter converts an uncompressed digital audio signal to an analog audio signal. The audio jack receives a stereo analog signal and outputs the stereo analog signal to an audio plug.
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公开(公告)号：US12126355B2
公开(公告)日：2024-10-22
申请号：US17859658
申请日：2022-07-07
申请人： Socionext Inc.
CPC分类号： H03M1/66 , H03M1/38 , H03M1/0604 , H03M1/12
摘要： Mixed-signal circuitry including a set of capacitive digital-to-analogue converter, CDAC, units for carrying out digital-to-analogue conversion operations to convert respective digital values into corresponding analogue values; and control circuitry, where: each CDAC unit includes an array of capacitors at least some of which are configured to be individually-switched dependent on the digital values, the capacitors configured to have nominal capacitances; a given capacitor of the array of capacitors in each of the CDAC units is a target capacitor; the set of CDAC units includes a plurality of sub-sets of CDAC units; at least one of the target capacitors per sub-set of CDAC units is a variable capacitor, controllable by the control circuitry to have any one of a plurality of nominal capacitances defined by the configuration of that capacitor.
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公开(公告)号：US12126350B2
公开(公告)日：2024-10-22
申请号：US17990737
申请日：2022-11-21
发明人： Ting-Hao Wang , Hui-Wen Tsai , Shih-Chun Lo
CPC分类号： H03M1/0604
摘要： A digital-to-analog converter and an operation method thereof are provided. The digital-to-analog converter includes a current source module, a decoder, a change indicator, and a random number generator. The decoder is coupled to the current source module and receives a digital input signal. The change indicator is coupled to the decoder and provides an indication signal to the decoder. The random number generator is coupled to the change indicator and provides a random number signal to the change indicator. The change indicator generates an indication signal according to the random number signal, and the decoder generates a control signal to the current source module according to the digital input signal and the indication signal, so that the current source module generates an analog output signal corresponding to the digital input signal according to the control signal.
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公开(公告)号：US12119833B2
公开(公告)日：2024-10-15
申请号：US17877375
申请日：2022-07-29
申请人： Analog Devices, Inc.
发明人： Khiem Quang Nguyen
CPC分类号： H03M1/0604 , H03M1/0665 , H03M1/66
摘要： Embodiments of the disclosure provide improved mismatch shaping for a digital to analog converter, the method including splitting an original input of a circuit into a plurality of time interleaved data streams; element rotation selection (ERS) logic to process the plurality of time interleaved data streams; and directing one of the plurality of time interleaved data streams to the ERS logic according to a decision of a data-weighted sigma-delta (SD) modulator. In other example implementations, the method can further include multiplexing one of the plurality of time interleaved data streams to be provided to a barrel shifter. In yet other examples, the method can include monitoring a difference between the plurality of time interleaved data streams as a basis for the directing such that a data sample rate for the digital to analog converter is reduced over a time interval.
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公开(公告)号：US12112258B2
公开(公告)日：2024-10-08
申请号：US18131949
申请日：2023-04-07
发明人： Vijay S. Ramesh , Richard C. Murphy
IPC分类号： G06N3/065 , G06F7/48 , G11C11/4063 , H03M1/12 , H03M1/66
CPC分类号： G06N3/065 , G06F7/48 , G11C11/4063 , H03M1/12 , H03M1/66
摘要： Systems, apparatuses, and methods related to a neuron built with posits are described. An example system may include a memory device and the memory device may include a plurality of memory cells. The plurality of memory cells can store data including a bit string in an analog format. A neuromorphic operation can be performed on the data in the analog format. The example system may include an analog to digital converter coupled to the memory device. The analog to digital converter may convert the bit string in the analog format stored in at least one of the plurality of memory cells to a format that supports arithmetic operations to a particular level of precision.
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公开(公告)号：US12107707B2
公开(公告)日：2024-10-01
申请号：US18217395
申请日：2023-06-30
申请人： Analog Bits Inc.
发明人： Michael A. Ang , Alan C. Rogers
CPC分类号： H04L25/03885 , H03M1/66 , H04L25/03006
摘要： A mixed signal receiver includes a first sample and hold (S/H) circuit having a first S/H input terminal to receive an analog input signal and a first S/H output terminal directly coupled to a first common node; a first data slicer having a first slicer input terminal coupled to the first common node; and a first data-driven charge coupling digital-to-analog converter (DAC) including: (i) a DAC input terminal to receive a first digital signal from a first digital output of the first data slicer, (ii) a DAC output terminal directly coupled to the first common node, (iii) a plurality of capacitor modules configured to be pre-charged during a sample phase, and (iv) logic components, wherein when the logic components toggle a voltage on the plurality of capacitor modules, charge is capacitively coupled to or from the first common node during an immediately subsequent hold phase.
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公开(公告)号：US12099569B2
公开(公告)日：2024-09-24
申请号：US18337955
申请日：2023-06-20
发明人： Xiaofeng Zhang , She-Hwa Yen
摘要： A method and circuit for performing vector operations may include, for each sequentially performed operation, operating a switch that corresponds to a current bit-order. Operating the switch may cause a value corresponding to an output of the operation to be stored on a capacitor corresponding to the current bit-order. A time interval during which the switch is operated may be non-uniform with respect to time intervals for other switches, and the time interval may be based at least in part on a settling time of the capacitor. The method may also include performing a bit-order weighted summation of values stored on the plurality of capacitors to generate a result of the vector operation.
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公开(公告)号：US20240275398A1
公开(公告)日：2024-08-15
申请号：US18426056
申请日：2024-01-29
发明人： Jingping GU , Yifei QIAN
IPC分类号： H03M1/66
CPC分类号： H03M1/66
摘要： This application provides a novel capacitive DAC structure, which at least includes a fully differential DAC capacitor array, a comparator, and a sampling and holding switch provided between the fully differential DAC capacitor array and the comparator. In this application, by providing the sampling and holding switch, including a first logic switch, a second logic switch and a third logic switch, between the fully differential DAC capacitor array and the comparator, and changing the timing relationship of the switches to generate a stable common mode level Vcm, the area and power consumption can be greatly reduced, the IP competitiveness can be effectively improved, and it can be used for high-performance ADC design.
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