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公开(公告)号：US20220113942A1
公开(公告)日：2022-04-14
申请号：US17092258
申请日：2020-11-07
发明人： She-Hwa Yen , Xiaofeng Zhang
摘要： A method and circuit for performing multi-layer vector-matrix multiplication operations may include, at a first multiplier-accumulator (MAC) layer, converting a digital input vector using one-bit digital to analog converters (DACs); sequentially performing vector-matrix multiplication operations for the analog DAC signals; and sequentially performing an analog-to-digital (ADC) operation on outputs of the vector-matrix multiplication operations to generate binary partial output vectors. At a second MAC layer, the method and circuit may sequentially receive the binary partial output vectors from the first MAC layer at multi-bit DACs; and sequentially perform vector-matrix multiplication operations to generate a summed binary output for the second MAC layer.
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公开(公告)号：US11922131B2
公开(公告)日：2024-03-05
申请号：US17092234
申请日：2020-11-07
发明人： Xiaofeng Zhang , She-Hwa Yen
CPC分类号： G06F7/5443 , G06F17/16 , H03M1/1205 , H03M1/74
摘要： A method for performing vector-matrix multiplication may include converting a digital input vector comprising a plurality of binary-encoded values into a plurality of analog signals using a plurality of one-bit digital to analog converters (DACs); sequentially performing, using an analog vector matrix multiplier and based on bit-order, vector-matrix multiplication operations using a weighting matrix for the plurality of analog signals to generate analog outputs of the analog vector matrix multiplier; sequentially performing an analog-to-digital (ADC) operation on the analog outputs of the analog vector matrix multiplier to generate binary partial output vectors; and combining the binary partial output vectors to generate a result of the vector-matrix multiplication.
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公开(公告)号：US20230334118A1
公开(公告)日：2023-10-19
申请号：US18337955
申请日：2023-06-20
发明人： Xiaofeng Zhang , She-Hwa Yen
摘要： A method and circuit for performing vector operations may include, for each sequentially performed operation, operating a switch that corresponds to a current bit-order. Operating the switch may cause a value corresponding to an output of the operation to be stored on a capacitor corresponding to the current bit-order. A time interval during which the switch is operated may be non-uniform with respect to time intervals for other switches, and the time interval may be based at least in part on a settling time of the capacitor. The method may also include performing a bit-order weighted summation of values stored on the plurality of capacitors to generate a result of the vector operation.
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公开(公告)号：US20220114233A1
公开(公告)日：2022-04-14
申请号：US17092227
申请日：2020-11-07
发明人： Xiaofeng Zhang , She-Hwa Yen
摘要： A method and circuit for performing vector-matrix multiplication may include converting an input vector of binary-encoded values into analog signals using one-bit DACs, and sequentially performing a vector-matrix multiplication operation for each bit-order. The method may also include, for each sequentially performed operation, operating a switch that corresponds to a current bit-order. Operating the switch may cause a value corresponding to an output of the multiplier to be stored on a capacitor corresponding to the current bit-order. A time interval during which the switch is operated may be non-uniform with respect to time intervals for other switches, and the time interval may be based at least in part on a settling time of the capacitor. The method may also include performing a bit-order weighted summation of values stored on the plurality of capacitors to generate a result of the vector-matrix multiplication.
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公开(公告)号：US20220113941A1
公开(公告)日：2022-04-14
申请号：US17092234
申请日：2020-11-07
发明人： Xiaofeng Zhang , She-Hwa Yen
摘要： A method for performing vector-matrix multiplication may include converting a digital input vector comprising a plurality of binary-encoded values into a plurality of analog signals using a plurality of one-bit digital to analog converters (DACs); sequentially performing, using an analog vector matrix multiplier and based on bit-order, vector-matrix multiplication operations using a weighting matrix for the plurality of analog signals to generate analog outputs of the analog vector matrix multiplier; sequentially performing an analog-to-digital (ADC) operation on the analog outputs of the analog vector matrix multiplier to generate binary partial output vectors; and combining the binary partial output vectors to generate a result of the vector-matrix multiplication.
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公开(公告)号：US12099569B2
公开(公告)日：2024-09-24
申请号：US18337955
申请日：2023-06-20
发明人： Xiaofeng Zhang , She-Hwa Yen
摘要： A method and circuit for performing vector operations may include, for each sequentially performed operation, operating a switch that corresponds to a current bit-order. Operating the switch may cause a value corresponding to an output of the operation to be stored on a capacitor corresponding to the current bit-order. A time interval during which the switch is operated may be non-uniform with respect to time intervals for other switches, and the time interval may be based at least in part on a settling time of the capacitor. The method may also include performing a bit-order weighted summation of values stored on the plurality of capacitors to generate a result of the vector operation.
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公开(公告)号：US12019702B2
公开(公告)日：2024-06-25
申请号：US17092258
申请日：2020-11-07
发明人： She-Hwa Yen , Xiaofeng Zhang
CPC分类号： G06F17/16 , G06F7/5443 , G06G7/16 , H03M1/74 , H03M1/1205
摘要： A method and circuit for performing multi-layer vector-matrix multiplication operations may include, at a first multiplier-accumulator (MAC) layer, converting a digital input vector using one-bit digital to analog converters (DACs); sequentially performing vector-matrix multiplication operations for the analog DAC signals; and sequentially performing an analog-to-digital (ADC) operation on outputs of the vector-matrix multiplication operations to generate binary partial output vectors. At a second MAC layer, the method and circuit may sequentially receive the binary partial output vectors from the first MAC layer at multi-bit DACs; and sequentially perform vector-matrix multiplication operations to generate a summed binary output for the second MAC layer.
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公开(公告)号：US11681776B2
公开(公告)日：2023-06-20
申请号：US17092227
申请日：2020-11-07
发明人： Xiaofeng Zhang , She-Hwa Yen
摘要： A method and circuit for performing vector-matrix multiplication may include converting an input vector of binary-encoded values into analog signals using one-bit DACs, and sequentially performing a vector-matrix multiplication operation for each bit-order. The method may also include, for each sequentially performed operation, operating a switch that corresponds to a current bit-order. Operating the switch may cause a value corresponding to an output of the multiplier to be stored on a capacitor corresponding to the current bit-order. A time interval during which the switch is operated may be non-uniform with respect to time intervals for other switches, and the time interval may be based at least in part on a settling time of the capacitor. The method may also include performing a bit-order weighted summation of values stored on the plurality of capacitors to generate a result of the vector-matrix multiplication.
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