公开(公告)号：US12231119B2

公开(公告)日：2025-02-18

申请号：US16834316

申请日：2020-03-30

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Steven Ernest Finn

IPC: H03K19/00 ,  H03K19/0175 ,  H03K19/0944

Abstract: A circuit includes a first transistor comprising a first control input and first and second current terminals, the first control input coupled to receive a first input control signal, and the first current terminal coupled to a first power supply node. The circuit also includes a first resistor coupled to the first control input of the first transistor, a first capacitor coupled between the second current terminal of the first transistor and the first resistor and a second transistor comprising a second control input and third and fourth current terminals, the third current terminal coupled to the first resistor and to the first capacitor.

公开(公告)号：US12224115B2

公开(公告)日：2025-02-11

申请号：US18170915

申请日：2023-02-17

Applicant: SEIKO EPSON CORPORATION

Inventor： Kei Ishimaru ,  Yoshihiko Nimura

IPC: H01F7/06 ,  H03F3/45 ,  H03K19/0175

Abstract: A current sense amplifier circuit of a circuit device includes: an operational amplifier; a first resistor provided between one end of a shunt resistor and a first node, a first switch provided between the first node and a first input node, a second resistor provided between another end of the shunt resistor and a second node, a second switch provided between the second node and a second input node, a third resistor provided between a constant voltage node and the third node, a third switch provided between the third node and the first input node, a fourth resistor provided between the constant voltage node and a fourth node, and a fourth switch provided between the fourth node and the second input node.

公开(公告)号：US12218666B1

公开(公告)日：2025-02-04

申请号：US18133413

申请日：2023-04-11

Applicant: Google LLC

Inventor： Michial Allen Gunter ,  Charles Henry Leichner, IV ,  Tammo Spalink

IPC: H03K19/17736 ,  G06F15/80 ,  G06N3/04 ,  G06N3/063 ,  G06N3/082 ,  H03K19/0175 ,  G06F15/76

Abstract: An application specific integrated circuit (ASIC) chip includes: a systolic array of cells; and multiple controllable bus lines configured to convey data among the systolic array of cells, in which the systolic array of cells is arranged in multiple tiles, each tile of the multiple tiles including 1) a corresponding subarray of cells of the systolic array of cells, 2) a corresponding subset of controllable bus lines of the multiple controllable bus lines, and 3) memory coupled to the subarray of cells.

公开(公告)号：US12203775B2

公开(公告)日：2025-01-21

申请号：US17769598

申请日：2020-10-29

Applicant: CANON KABUSHIKI KAISHA

Inventor： Kohichi Nakamura ,  Masaki Sato ,  Daisuke Kobayashi ,  Tetsuya Itano ,  Daisuke Yoshida

IPC: G01C3/02 ,  H03F3/45 ,  H03K17/687 ,  H03K19/0175 ,  H04L25/02 ,  H04N25/709 ,  H04N25/78

Abstract: The disclosed apparatus includes a plurality of differential transmitters, and a power supply circuit that supplies a power supply voltage to each of the plurality of differential transmitters. The power supply circuit includes a common circuit unit that defines the power supply voltage supplied to the plurality of differential transmitters, and a plurality of individual circuit units provided in association with the plurality of differential transmitters and each connected to the common circuit unit. Each of the plurality of individual circuit units has an output node that outputs the power supply voltage defined by the common circuit unit to a corresponding differential transmitter of the plurality of differential transmitters, and respective output nodes of the plurality of individual circuit units are connected to each other.

公开(公告)号：US12199614B2

公开(公告)日：2025-01-14

申请号：US18081922

申请日：2022-12-15

Applicant: Beijing ESWIN Computing Technology Co., Ltd. ,  Hefei ESWIN Computing Technology Co., Ltd.

Inventor： Xiaoheng Zhang ,  Jiajhang Wu ,  Haohao Zhang

IPC: H03K19/0175 ,  H03K3/356 ,  H03K19/0185 ,  H03M1/66

Abstract: The present application provides a level shift circuit, an integrated circuit, and an electronic device. The level shift circuit comprises: an input module, configured to output a first control signal according to a first power supply voltage signal, first and second input voltages, inverted voltages of the first and second input voltages that received; a control voltage generation module, configured to receive the first control signal, and generate a plurality of node voltages according to the first control signal and a second power supply voltage signal; and output control modules, configured to generate first to fourth output signals according to the node voltages and the first power supply voltage signal, or generate fifth to eighth output signals according to the second power supply voltage signal and the node voltages.

公开(公告)号：US20250015800A1

公开(公告)日：2025-01-09

申请号：US18772911

申请日：2024-07-15

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Wan-Yen Lin ,  Chia-Hui Chen ,  Chia-Jung Chang

IPC: H03K17/689 ,  H03K3/356 ,  H03K19/0175 ,  H03K19/0185

Abstract: A level shifter includes an input circuit having first and second input terminals configured to receive complementary input signals at a first voltage level and a second voltage level. A cross-latch circuit is coupled to the input circuit, and has first and second output terminals configured to provide complementary output signals at a third voltage level and a fourth voltage level. The input circuit includes first and second control nodes configured to output first and second control signals at the first voltage level and the fourth voltage level based on the input signals. A tracking circuit is coupled to the input circuit and the cross-latch circuit, and is configured to input first and second tracking signals to the cross-latch circuit based on the first and second control signals, wherein the first tracking signal is the greater of the first control signal and the third voltage level, and the second tracking signal is the greater of the second control signal and the third voltage level.

公开(公告)号：US12176895B2

公开(公告)日：2024-12-24

申请号：US17715049

申请日：2022-04-07

Applicant: Airoha Technology (HK) Limited

Inventor： Huan-Sheng Chen

IPC: H04B17/00 ,  G06F13/42 ,  H03K5/133 ,  H03K19/0175 ,  H04L1/24

Abstract: A dummy signal generation circuit includes a consecutive identical digit (CID) detection circuit and a dummy transition circuit. The CID detection circuit detects occurrence of N CIDs in serial data, and sets a transition enable window in response to each sequence of N CIDs in the serial data, where N is a positive integer not smaller than 3. The dummy transition circuit generates a dummy signal that has transitions constrained to occur within transition enable windows set by the CID detection circuit.

公开(公告)号：US20240413817A1

公开(公告)日：2024-12-12

申请号：US18611763

申请日：2024-03-21

Applicant: SHEN AN MICRO CO.LTD

Inventor： Mengzhao WEI

IPC: H03K17/16 ,  H03K19/0175 ,  H03F3/45

Abstract: A Correlated Double Sampling (CDS) integrating circuit and a data converter, the CDS circuit includes a CDS integration module and a level shifting module. The CDS integration module is configured to sample a first input signal and an Operational Amplifier (Opamp) input offset voltage to a sampling capacitor during a first phase; and sample a second input signal and the Opamp input offset voltage to the sampling capacitor during a second phase, and transfer a charge difference generated on the sampling capacitor to an integrating capacitor. The level shifting module is configured to sample an output signal and a common-mode voltage to a level shifting capacitor during a first stage of the first phase and the second phase, and shift a potential of an Opamp output voltage towards the common-mode voltage through the level shifting capacitor in a second stage of the second phase.

公开(公告)号：US12155378B2

公开(公告)日：2024-11-26

申请号：US18128664

申请日：2023-03-30

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD. ,  TSMC CHINA COMPANY, LIMITED

Inventor： Zhen Tang ,  Lei Pan ,  Miranda Ma

IPC: H03K17/16 ,  H03K5/12 ,  H03K17/14 ,  H03K17/687 ,  H03K19/0175

Abstract: In a method of operating a circuit, at a beginning of a first edge of a driving signal, a first transistor is turned ON to pull, at a first changing rate, a voltage of the driving signal on the first edge from a first voltage toward a second voltage. Then, in response to the voltage of the driving signal on the first edge reaching a threshold voltage between the first voltage and the second voltage, the first transistor is turned OFF and an output circuit is caused to start a second edge of an output signal in response to the first edge of the driving signal. The second edge has a slew rate corresponding to a second changing rate of the voltage of the driving signal on the first edge from the threshold voltage toward the second voltage. The second changing rate is smaller than the first changing rate.

公开(公告)号：US20240388288A1

公开(公告)日：2024-11-21

申请号：US18788634

申请日：2024-07-30

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Yung-Shun Chen ,  Chin-Chiang Chang ,  Yung-Chow Peng

IPC: H03K17/687 ,  H03K19/0175 ,  H03K19/0185 ,  H03K19/20

Abstract: A device including an inverter circuit, a hysteresis control circuit, and a high-side input level shifter. The inverter circuit having an output and including at least two series connected PMOS transistors connected, at the output, in series to at least two series connected NMOS transistors. The hysteresis control circuit coupled to the output to provide feedback to the at least two series connected PMOS transistors and to the at least two series connected NMOS transistors. The high-side input level shifter connected to gates of the at least two PMOS transistors and configured to shift a low level of an input signal to a higher level and provide the higher level to one or more of the gates of the at least two PMOS transistors.