公开(公告)号：US12068740B2

公开(公告)日：2024-08-20

申请号：US18226278

申请日：2023-07-26

申请人： REALTEK SEMICONDUCTOR CORPORATION

发明人： Yen-Ting Wu

IPC分类号： H03K17/687 ,  H03K17/04 ,  H03K19/01

CPC分类号： H03K17/04 ,  H03K19/01

摘要： A bootstrapped switch includes a first transistor, a second transistor, a first capacitor, three switches, and a switch circuit. The switch circuit includes a first switch, a second switch, a third switch, a fourth switch, a fifth switch, a sixth switch, and a second capacitor. The first transistor receives the input voltage and outputs the output voltage. The first terminal of the second transistor receives the input voltage, and the second terminal of the second transistor is coupled to the first capacitor. The control terminal of the first switch receives a clock. The second switch is coupled between the control terminal of the first transistor and the first switch. The second capacitor is coupled to a reference voltage through the third switch and the sixth switch, coupled to the input voltage through the fifth switch, and coupled to the control terminal of the first transistor through the fourth switch.

公开(公告)号：US11522544B2

公开(公告)日：2022-12-06

申请号：US16878233

申请日：2020-05-19

申请人： Rambus Inc.

发明人： Huy M. Nguyen ,  Vijay Gadde ,  Benedict Lau

IPC分类号： H03K19/00 ,  H03K19/01 ,  H04L25/02 ,  H03K5/24 ,  H03K21/08

摘要： Described are on-die termination (ODT) systems and methods that facilitate high-speed communication between a driver die and a receiver die interconnected via one or more signal transmission lines. An ODT control system in accordance with one embodiment calibrates and maintains termination resistances and drive currents to produce optimal output swing voltages. Comparison circuitry employed to calibrate the reference resistance is also used to calibrate the drive current. Termination elements in some embodiments are divided into two adjustable resistive portions, both of which are designed to minimize capacitive loading. One portion is optimized to produce a relatively high range of adjustment, while the other is optimized for fine-tuning and glitch-free switching.

公开(公告)号：US10270441B2

公开(公告)日：2019-04-23

申请号：US15685230

申请日：2017-08-24

申请人： Rambus Inc.

发明人： Huy M. Nguyen ,  Vijay Gadde ,  Benedict Lau

IPC分类号： H03K19/00 ,  H03K5/24 ,  H03K19/01 ,  H04L25/02 ,  H03K21/08

摘要： Described are on-die termination (ODT) systems and methods that facilitate high-speed communication between a driver die and a receiver die interconnected via one or more signal transmission lines. An ODT control system in accordance with one embodiment calibrates and maintains termination resistances and drive currents to produce optimal output swing voltages. Comparison circuitry employed to calibrate the reference resistance is also used to calibrate the drive current. Termination elements in some embodiments are divided into two adjustable resistive portions, both of which are designed to minimize capacitive loading. One portion is optimized to produce a relatively high range of adjustment, while the other is optimized for fine-tuning and glitch-free switching.

公开(公告)号：US10148261B1

公开(公告)日：2018-12-04

申请号：US15845466

申请日：2017-12-18

申请人： NXP USA, Inc.

发明人： Srikanth Jagannathan ,  Kumar Abhishek

IPC分类号： H03K19/01 ,  H03K19/09 ,  H04B1/04 ,  H03K3/00 ,  H04L25/02 ,  H03K17/16 ,  H03K5/159 ,  H03K19/21

摘要： A low voltage differential signaling (LVDS) driver circuit, system, apparatus, and methodology are provided for controlling switching components in a primary current stage and a pre-emphasis current stage with an adaptive pre-emphasis gain tuning hardware control circuit arranged to provide control signals for periodically tuning a pre-emphasis gain setting for the secondary pre-emphasis current stage by selecting an optimum pre-emphasis gain setting from a plurality of pre-emphasis gain setting which minimizes an inter-symbol interference (ISI) jitter measure for the LVDS driver circuit.

公开(公告)号：US10033391B2

公开(公告)日：2018-07-24

申请号：US15095439

申请日：2016-04-11

申请人： Avago Technologies General IP (Singapore) Pte. Ltd.

发明人： Paul Penzes ,  Mark Fullerton

IPC分类号： G06F1/32 ,  H03L7/08 ,  H03K3/03 ,  H03K3/037 ,  H03K19/01 ,  G06F12/14 ,  G06F21/44 ,  H03K5/133 ,  H03L7/097 ,  H03L7/099 ,  G06F1/26 ,  H03K5/00

摘要： Adaptive clocking schemes for synchronized on-chip functional blocks are provided. The clocking schemes enable synchronous clocking which can be adapted according to changes in signal path propagation delay due temperature, process, and voltage variations, for example. In embodiments, the clocking schemes allow for the capacity utilization of a logic path to be increased.

公开(公告)号：US09935634B2

公开(公告)日：2018-04-03

申请号：US14327004

申请日：2014-07-09

申请人： ARM Limited

发明人： David Walter Flynn ,  James Edward Myers

IPC分类号： H03K19/01 ,  H03K19/0175

CPC分类号： H03K19/017509

摘要： An integrated circuit including a first voltage domain incorporates real time clock circuitry that communicates via communication circuitry with processing circuitry contained within a second voltage domain. The communication circuitry includes first parallel-to-serial conversion circuitry located within the first voltage domain, level shifting circuitry for passing serial signals between the voltage domains and second parallel-to-serial circuitry located in the second voltage domain.

公开(公告)号：US20180062820A1

公开(公告)日：2018-03-01

申请号：US15679739

申请日：2017-08-17

申请人： Sinclair Broadcast Group, Inc.

发明人： Michael J. SIMON

IPC分类号： H04L5/00 ,  H03K19/01 ,  H04L5/22 ,  H04L27/26

CPC分类号： H04L5/0083 ,  G06F17/142 ,  H03K19/01 ,  H04L5/0007 ,  H04L5/0044 ,  H04L5/0048 ,  H04L5/22 ,  H04L27/2666 ,  H04W76/15

摘要： Apparatuses and methods are provided for generating, transmitting, receiving, and decoding one or more band segmented bootstrap signals and one or more corresponding partitioned post bootstrap signals. For example, a transmitter is configured to generate a first set of symbols and a second set of symbols, where the first set of symbols includes information about the second set of symbols. The transmitter is further configured to generate a third set of symbols and a fourth set of symbols, where the third set of symbols includes information about the fourth set of symbols. The transmitter is also configured to generate a data frame including the first, second, third, and fourth set of symbols. A bandwidth of the data frame includes a first segment and a second segment.

公开(公告)号：US20180018257A1

公开(公告)日：2018-01-18

申请号：US15590081

申请日：2017-05-09

申请人： Renesas Electronics Corporation

发明人： Takeo MIKI

IPC分类号： G06F12/02 ,  H03K19/01 ,  G06F17/30 ,  H04L12/28 ,  H03K19/21

CPC分类号： G06F12/0215 ,  G06F17/30 ,  G06F17/30982 ,  H03K19/01 ,  H03K19/21 ,  H04L12/28

摘要： To provide a search device with less memory consumption, the search device includes a first associative memory searched with a first search key, a second associative memory searched with a second search key, a concatenated search data generating unit that generates first search information based on hit information including multiple hits in the first associative memory, and a search key generating unit that includes a first key generating unit generating a portion of search data as the first search key and a second search key generating unit generating the first search information and another portion of the search data as the second search key.

公开(公告)号：US09438835B2

公开(公告)日：2016-09-06

申请号：US14602924

申请日：2015-01-22

申请人： Sony Corporation

发明人： Yusuke Oike

IPC分类号： H04N5/372 ,  G11C7/12 ,  G11C8/08 ,  G11C11/408 ,  H03K3/356 ,  H03K17/04 ,  H03K19/01 ,  H04N5/374 ,  H04N5/378

CPC分类号： H04N5/372 ,  G11C7/12 ,  G11C8/08 ,  G11C11/4085 ,  H03K3/356165 ,  H03K17/04 ,  H03K19/01 ,  H04N5/374 ,  H04N5/378

摘要： A semiconductor device is provided which has a driving circuit operable to drive a circuit that has a delay, the semiconductor device including: an auxiliary driving circuit operable to accelerate drive of the driving circuit, which receives a drive signal of the driving circuit as an input signal.

摘要翻译： 提供一种半导体器件，其具有可操作以驱动具有延迟的电路的驱动电路，所述半导体器件包括：辅助驱动电路，其可操作以加速驱动电路的驱动，所述驱动电路接收驱动电路的驱动信号作为输入 信号。

公开(公告)号：US09373570B2

公开(公告)日：2016-06-21

申请号：US14267513

申请日：2014-05-01

申请人： DENSO CORPORATION

发明人： Hideki Kawahara ,  Takanori Imazawa

IPC分类号： H01L23/495 ,  H03K19/01 ,  H03K17/04 ,  H01L23/00

CPC分类号： H01L23/49562 ,  H01L23/495 ,  H01L24/36 ,  H01L24/37 ,  H01L24/40 ,  H01L2224/371 ,  H01L2224/37599 ,  H01L2224/40137 ,  H01L2224/48091 ,  H01L2224/48095 ,  H01L2224/48247 ,  H01L2224/73221 ,  H01L2224/83801 ,  H01L2224/84801 ,  H01L2924/00014 ,  H01L2924/12035 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/181 ,  H03K17/04 ,  H03K19/01 ,  H01L2924/00 ,  H01L2924/00012

摘要： A semiconductor module includes: a semiconductor element; first and second main current passages for energizing the semiconductor element, the first and second main current passages being opposed to each other in such a manner that a first energization direction of the first main current passage is opposite to a second energization direction of the second main current passage, or an angle between the first energization direction and the second energization direction is an obtuse angle; and a coil unit sandwiched between the first and second main current passages. The coil unit includes a coil, which generates an induced electromotive force when a magnetic flux interlinks with the coil, the magnetic flux being generated when current flows through the first and second main current passages.

摘要翻译： 半导体模块包括：半导体元件; 用于激励半导体元件的第一和第二主电流通道，第一和第二主电流通道彼此相对，使得第一主电流通道的第一通电方向与第二主电流通道的第二通电方向相反 或者第一通电方向与第二通电方向之间的角度为钝角; 以及夹在第一和第二主电流通道之间的线圈单元。 线圈单元包括线圈，该线圈当磁通量与线圈相互连接时产生感应电动势，当电流流过第一和第二主电流通道时产生磁通量。