公开(公告)号：US10033391B2

公开(公告)日：2018-07-24

申请号：US15095439

申请日：2016-04-11

Applicant: Avago Technologies General IP (Singapore) Pte. Ltd.

Inventor： Paul Penzes ,  Mark Fullerton

IPC: G06F1/32 ,  H03L7/08 ,  H03K3/03 ,  H03K3/037 ,  H03K19/01 ,  G06F12/14 ,  G06F21/44 ,  H03K5/133 ,  H03L7/097 ,  H03L7/099 ,  G06F1/26 ,  H03K5/00

Abstract: Adaptive clocking schemes for synchronized on-chip functional blocks are provided. The clocking schemes enable synchronous clocking which can be adapted according to changes in signal path propagation delay due temperature, process, and voltage variations, for example. In embodiments, the clocking schemes allow for the capacity utilization of a logic path to be increased.