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1.
公开(公告)号:US20240313765A1
公开(公告)日:2024-09-19
申请号:US18571215
申请日:2022-06-23
发明人: HIROKI AKASHI , YOHSUKE MITANI , YUTA NAGATOMI , MASAFUMI NAKAMURA , MASATOSHI NAKASE , KINYA KATO , YASUHIRO IIJIMA
IPC分类号: H03K17/30 , H03K17/06 , H03K17/081
CPC分类号: H03K17/302 , H03K17/063 , H03K17/08104 , H03K2217/0081
摘要: In a backup power supply system according to the present invention, in a non-defective state in which a main power supply is not defective, a controller turns on a first field-effect transistor and causes a third field-effect transistor to operate in an active region so as to charge the power storage device from the main power supply via a charging path through the first field-effect transistor, the second field-effect transistor, and the third field-effect transistor. In a defective state in which the main power supply is defective, the controller turns off the first field-effect transistor and turns on the second field-effect transistor and the third field-effect transistor so as to supply power from the power storage device to the load.
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公开(公告)号:US20240291475A1
公开(公告)日:2024-08-29
申请号:US18456529
申请日:2023-08-28
申请人: SK hynix Inc.
发明人: Seung Ho LEE
IPC分类号: H03K17/081
CPC分类号: H03K17/08104
摘要: An output driver includes a pull-up driving circuit coupled between a supply voltage terminal and an output pad, and configured to perform a pull-up operation on the output pad, a pull-down driving circuit coupled between the output pad and a ground terminal, and configured to perform a pull-down operation on the output pad, and a high voltage protection circuit including a resistor string and a transistor that are coupled in series between the output pad and the ground terminal.
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公开(公告)号:US12074589B2
公开(公告)日:2024-08-27
申请号:US17939790
申请日:2022-09-07
发明人: Junichi Chisaka
IPC分类号: H03K17/06 , H03K17/081
CPC分类号: H03K17/063 , H03K17/08104
摘要: According to one embodiment, a semiconductor device includes a first transistor, a first circuit, a second circuit, and a third circuit. The first transistor has one end connected to a power supply voltage terminal, the other end connected to a first node, and a gate connected to a first output terminal. The first circuit is configured to control a voltage of the first node based on a voltage of a ground voltage terminal. The second circuit is configured to control a voltage of the first output terminal based on the voltage of the ground voltage terminal and a voltage of an input terminal. The third circuit is configured to control switching between connection and disconnection between the ground voltage terminal and the first circuit.
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公开(公告)号:US20240283439A1
公开(公告)日:2024-08-22
申请号:US18424266
申请日:2024-01-26
申请人: ROHM CO., LTD.
发明人: Kenji HAMA , Takahiro KOTANI
IPC分类号: H03K17/081 , H02M1/08 , H03K17/06
CPC分类号: H03K17/08104 , H02M1/08 , H03K17/063
摘要: For example, the switching drive device 100 includes a driver 30 configured to drive an N-type semiconductor switch element, a current limiter 50 configured to limit a current fed to a boot capacitor BC1 included in a bootstrap circuit BTC, and a current controller 60 configured to control the operation of the current limiter 50. The current controller 60 is configured to drive the current limiter 50 to limit the current fed to the boot capacitor BC1 when the charge voltage across the boot capacitor BC1 is higher than a threshold value.
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公开(公告)号:US20240249982A1
公开(公告)日:2024-07-25
申请号:US18438338
申请日:2024-02-09
IPC分类号: H01L21/84 , H01L21/8234 , H01L23/00 , H01L23/31 , H01L23/66 , H01L27/092 , H01L27/12 , H01L29/417 , H03K17/081
CPC分类号: H01L21/84 , H01L23/66 , H01L27/1203 , H01L29/41733 , H03K17/08104 , H01L21/823456 , H01L23/3121 , H01L24/06 , H01L24/48 , H01L27/092 , H01L2224/04042 , H01L2224/05554 , H01L2224/06135 , H01L2224/45099 , H01L2224/48091 , H01L2224/48227 , H01L2924/00014 , H01L2924/1306 , H01L2924/13091 , H01L2924/14215 , H01L2924/15192 , H01L2924/15313 , H01L2924/181 , H01L2924/19105
摘要: Radio-frequency (RF) switching devices having improved voltage handling capability. In some embodiments, a switching device can include a first terminal and a second terminal, and a plurality of switching elements connected in series to form a stack between the first terminal and the second terminal. The switching elements can have a non-uniform distribution of a parameter that results in the stack having a first voltage handling capacity that is greater than a second voltage handling capacity corresponding to a similar stack having a substantially uniform distribution of the parameter.
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公开(公告)号:US12044766B2
公开(公告)日:2024-07-23
申请号:US17840542
申请日:2022-06-14
发明人: Kuo-Heng Chao , Chia-Hsiang Chuang , Ming-Jen Chao
IPC分类号: G01R31/28 , G01R19/00 , G01R35/00 , H02H1/00 , H02H3/04 , H02H3/10 , H02H7/08 , H02K11/33 , H02P6/20 , H02P6/24 , H02P27/06 , H03K17/081 , H03K17/687 , H02P6/182
CPC分类号: G01R35/00 , G01R19/0038 , G01R31/2837 , G01R31/2839 , H02H1/0007 , H02H3/044 , H02H3/10 , H02H7/08 , H02K11/33 , H02P6/20 , H02P6/24 , H02P27/06 , H03K17/08104 , H03K17/687 , H02P6/182
摘要: The present disclosure a program burning device configured to read or write to a program burning interface. The program burning device includes a microprocessor, a programming drive circuit and an overcurrent protection circuit. The microprocessor outputs a first test signal or a second test signal. The programming drive circuit outputs a high driving voltage or a low driving voltage to the program burning interface. After the programming drive circuit outputs the low driving voltage for a preset time, the programming drive circuit outputs the high driving voltage to make the program burning interface form a high impedance. Afterwards, the overcurrent protection circuit receives the first test signal to trigger the overcurrent protection, and then receives the second test signal to trigger the undercurrent protection. If triggering the overcurrent protection and the undercurrent protection are continuously failed over a preset number of times, the microprocessor determines that current protection is failed.
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7.
公开(公告)号:US20240243740A1
公开(公告)日:2024-07-18
申请号:US18620740
申请日:2024-03-28
申请人: Altera Corporation
发明人: Chee Hong Aw
IPC分类号: H03K17/081 , H04B1/12
CPC分类号: H03K17/08104 , H04B1/12
摘要: Integrated circuit devices, methods, and circuitry for selectively blocking a voltage signal on receiver circuitry to reduce or eliminate unequal aging on the receiver circuitry. A device may include a first input/output (IO) pin to receive a first voltage and a second IO pin to receive a second voltage. The device may include a differential signal receiver that includes a first terminal coupled to the first IO pin and a second terminal coupled to the second IO pin. Transmission gate circuitry may selectively block the first voltage or the second voltage from being applied to the differential signal receiver. The transmission gate circuitry may include transistors having a lower junction voltage limit than the first voltage or the second voltage, or both.
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公开(公告)号:US20240234411A1
公开(公告)日:2024-07-11
申请号:US18617658
申请日:2024-03-27
发明人: MING-FANG LAI , LIANG-YU SU , HANG FAN
IPC分类号: H01L27/02 , H01L27/06 , H02H9/04 , H03K17/081 , H01L29/20 , H01L29/778
CPC分类号: H01L27/0266 , H01L27/0285 , H01L27/0288 , H01L27/0605 , H01L27/0629 , H02H9/046 , H03K17/08104 , H01L29/2003 , H01L29/778 , H02H9/04 , H02H9/044
摘要: The present disclosure provides an electrostatic discharge (ESD) protection circuit, coupled between a first reference terminal and a second reference terminal; the ESD protection circuit includes a first voltage divider, a second voltage divider, a first trigger circuit, a second trigger circuit, a first discharge component and a second discharge component. The first trigger circuit includes a first GaN based transistor, including a first source/drain and a second source/drain coupled to the first reference terminal and a gate coupled to the second reference terminal via the first voltage divider. The second trigger circuit includes a terminal coupled to the first reference terminal via the second voltage divider. The first discharge component includes a gate coupled between the first trigger circuit and the first voltage divider. The second discharge component includes a gate coupled between the second trigger circuit and the second voltage divider.
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公开(公告)号:US12034438B2
公开(公告)日:2024-07-09
申请号:US17747198
申请日:2022-05-18
申请人: DENSO CORPORATION
发明人: Masahiro Yamamoto , Akimasa Niwa
IPC分类号: H03K17/687 , H03K17/00 , H03K17/081 , H03K17/082 , H03K17/18
CPC分类号: H03K17/687 , H03K17/002 , H03K17/08104 , H03K17/0822 , H03K17/18 , H01L2924/19041 , H03K2217/0054
摘要: A signal detection circuit includes: a voltage dividing circuit having at least a first pair of voltage dividing capacitors connected in series for dividing an input voltage and configured to output a divided voltage, and a detection circuit configured to detect the divided voltage. The first pair of voltage dividing capacitors are included in one semiconductor device. The semiconductor device includes: (i) a semiconductor substrate, (ii) a first conductor layer, (iii) a first dielectric layer, (iv) a second conductor layer, (v) a second dielectric layer, (vi) a third conductor layer, and (vii) a short-circuit portion configured to short-circuit the first conductor layer and the semiconductor substrate.
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10.
公开(公告)号:US20240213976A1
公开(公告)日:2024-06-27
申请号:US18372608
申请日:2023-09-25
发明人: Dongming Liu
IPC分类号: H03K17/081 , H03K17/687
CPC分类号: H03K17/08104 , H03K17/687 , H03K2217/0027 , H03K2217/0063
摘要: A calibration method includes obtaining an offset error of the overcurrent protection circuit by changing a current limiting state of the overcurrent protection circuit, adjusting an offset compensation circuit to calibrate the offset error of the overcurrent protection circuit and adjusting a gain calibration circuit based on the current limiting state of the overcurrent protection circuit to calibrate a gain error of the overcurrent protection circuit, wherein the overcurrent protection circuit comprises a first transistor, a second transistor, a third transistor, a first operational amplifier, a gain calibration circuit, an offset compensation circuit, and a driving circuit, and wherein the driving circuit is configured to receive a signal generated by the gain calibration circuit and generate a gate drive signal applied the first transistor and the third transistor.
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