公开(公告)号：US20240333280A1

公开(公告)日：2024-10-03

申请号：US18616703

申请日：2024-03-26

Applicant: ROHM CO., LTD.

Inventor： Suzunosuke KIMURA ,  Kosuke YASUJI ,  Hiroki SUGAMOTO

IPC: H03K17/30 ,  H02M3/07 ,  H03K17/041

CPC classification number: H03K17/302 ,  H02M3/07 ,  H03K17/04106 ,  H03K2217/0063 ,  H03K2217/0072

Abstract: The present disclosure provides a motor driver circuit. The motor driver circuit includes a high-side driver that drives a high-side transistor according to a control signal. The high-side driver includes a voltage monitoring circuit, a timer circuit and a charge pump circuit. The voltage monitoring circuit asserts a detection signal when a detection voltage of the high-side transistor becomes lower than a threshold value. The timer circuit starts measuring a predetermined time in response to the control signal changing to an on state that the high side transistor is instructed to turn on, or in response to an assertion of the detection signal when the control signal is in the on state. The charge pump circuit is active while the timer circuit measures the predetermined time, generates a boosted voltage in response to a clock signal and supplies the boosted voltage to a gate of the high-side transistor.

公开(公告)号：US20230421145A1

公开(公告)日：2023-12-28

申请号：US17849676

申请日：2022-06-26

Applicant: Wolfspeed, Inc.

Inventor： Blake Whitmore Nelson ,  Brian DeBoi ,  Daniel John Martin

IPC: H03K17/041 ,  H03K17/687

CPC classification number: H03K17/04106 ,  H03K17/687 ,  H03K2217/0072 ,  H03K2217/0063

Abstract: The present disclosure relates to a power module with a power path extending through a first field-effect transistor (FET) and a second FET. A primary conductive structure connecting the first FET and the second FET in series provides a primary parasitic inductor within the power path. A first secondary conductive structure connected to both a gate and a source of the first FET provides a first secondary parasitic inductor within a first gate path, and a second secondary conductive structure connected to both a gate and a source of the second FET provides a second secondary parasitic inductor within a second gate path. The first secondary conductive structure and the second secondary conductive structure are configured such that mutual coupling between the first secondary parasitic inductor and the primary parasitic inductor and mutual coupling between the second secondary parasitic inductor and the primary parasitic inductor are substantially symmetrical.

公开(公告)号：US11683028B2

公开(公告)日：2023-06-20

申请号：US17466322

申请日：2021-09-03

Applicant: NXP USA, Inc.

Inventor： Venkata Naga Koushik Malladi

IPC: H03K17/00 ,  H03K17/041 ,  H04B1/44

CPC classification number: H03K17/04106 ,  H04B1/44

Abstract: Embodiments described herein include radio frequency (RF) switches that may provide increased power handling capability. In general, the embodiments described herein can provide this increased power handling by equalizing the voltages across transistors when the RF switch is open. Specifically, the embodiments described herein can be implemented to equalize the source-drain voltages across each field effect transistor (FET) in a FET stack that occurs when the RF switch is open and not conducting current. This equalization can be provided by using one or more compensation circuits to couple one or more gates and transistor bodies in the FET stack in a way that at least partially compensates for the effects of parasitic leakage currents in the FET stack. In addition, multiple FET stacks are implemented in parallel in at least some switch branches to improve settling time for the branch.

公开(公告)号：US11677394B2

公开(公告)日：2023-06-13

申请号：US17395499

申请日：2021-08-06

Applicant: REALTEK SEMICONDUCTOR CORPORATION

Inventor： Ming-Hui Tung

IPC: H03K17/10 ,  H03K17/30 ,  H03K17/04 ,  G06F13/38 ,  H03K17/041

CPC classification number: H03K17/102 ,  G06F13/382 ,  H03K17/04106 ,  H03K17/302

Abstract: The present invention discloses a signal output apparatus. Each of two output circuits includes an inverter including an input terminal and an output terminal, and a resistor coupled between the output terminal and a differential output terminal. Each of MOS capacitors is coupled between the output terminals. Under a first operation mode, two current supplying circuits are disabled. The input terminals respectively receive a high and a low state input voltages and the output terminals generate a low and a high state output voltages. The capacitances become larger than a predetermined level. Under a second operation mode, one of the current supplying circuits is enabled to output a supplying current to the differential output terminal. The input terminals receive the high state input voltage. The output terminals generate the low state output voltage. The capacitances become not larger than the predetermined level.

公开(公告)号：US11677392B2

公开(公告)日：2023-06-13

申请号：US17233415

申请日：2021-04-16

Applicant: Analog Devices International Unlimited Company

Inventor： Ercan Kaymaksut ,  Mehmet Arda Akkaya ,  Murat Davulcu ,  Turusan Kolcuoglu

IPC: H03K17/06 ,  H03K17/041 ,  H03K17/10 ,  H03K17/693

CPC classification number: H03K17/04106 ,  H03K17/063 ,  H03K17/102 ,  H03K17/693

Abstract: Passive gate bias network topologies are implemented for stacked FET switch structures, which improve the settling time and low cut-off frequency for both DC and non-DC operation. DC capable stacked switch bias structures provide gate and bulk bias voltages, using input DC voltages, which are coupled to the gate terminals and the bulk terminals of the stacked switches. The DC coupling can be achieved using resistors, or a combination of resistors and diodes. An exemplary SPST switch includes a series stacked switch in combination with a shunt stacked switch, which can be controlled between alternating states. For low cut-off frequency improvement structures, an input signal is coupled to the gate terminals and bulk terminals of the switches in the stacked switches, using a DC block capacitor and resistors. The low cut-off of the bulk can be improved by connecting the bulk terminal of one switch to the opposite polarity switch.

公开(公告)号：US11671093B2

公开(公告)日：2023-06-06

申请号：US17655367

申请日：2022-03-18

Applicant: Delta Electronics (Shanghai) Co., Ltd.

Inventor： Jie Dong ,  Zhenqing Xu ,  Weiqiang Zhang

IPC: H03K17/04 ,  H03K17/041 ,  H03K17/567 ,  H03K17/687 ,  H02M1/08 ,  H02M3/158 ,  H02M3/337 ,  H03K17/06

CPC classification number: H03K17/687 ,  H02M3/337 ,  H03K17/04106 ,  H03K17/06 ,  H03K2217/009

Abstract: The present invention provides a driving device and a control method. The driving device is configured to drive a power switch and includes a power supply, a first bridge arm coupled to the power supply, a second bridge arm coupled in parallel to the first bridge arm, and a resonant inductor. The first bridge arm includes a first switch and a second switch connected to a first midpoint, the second bridge arm comprises a first semiconductor element and a second semiconductor element connected to a second midpoint, and the resonant inductor is coupled between the first midpoint and the second midpoint. The control method includes turning on the first switch for a first period such that the power supply charges a gate electrode of the power switch; and in response to a decrease of a current of the resonant inductor to a first threshold value, turning on the first switch again for a second period such that a potential of the first midpoint is equal to a potential of the second midpoint.

公开(公告)号：US11632107B1

公开(公告)日：2023-04-18

申请号：US17492180

申请日：2021-10-01

Applicant: pSemi Corporation

Inventor： Ravindranath D. Shrivastava ,  Alper Genc

IPC: H03K17/16 ,  H03K17/041 ,  H03K17/0412 ,  H03K17/693 ,  H04B1/44 ,  H03K17/687 ,  H03K17/06 ,  H01L27/06

Abstract: A FET switch stack has a stacked arrangement of FET switches, a gate resistor network with ladder resistors and common gate resistors, and a gate resistor bypass arrangement. The bypass arrangement has a first set of bypass switches connected across the gate resistors and a second set of bypass switches connected across the ladder resistors. Bypass occurs during at least a portion of the transition state of the stacked arrangement of FET switches.

公开(公告)号：US20230097937A1

公开(公告)日：2023-03-30

申请号：US17670099

申请日：2022-02-11

Applicant: Kabushiki Kaisha Toshiba ,  Toshiba Electronic Devices & Storage Corporation

Inventor： Satoshi KURACHI

IPC: H03K17/041 ,  H03K17/687 ,  H03K17/10

Abstract: A switch circuit of an embodiment includes a radio-frequency switch and a level shifter circuit. The radio-frequency switch, which includes a first switch group and a second switch group each including a plurality of switches, switches transmission/reception of a radio-frequency signal. The level shifter circuit outputs a first signal for controlling ON/OFF of each switch of the first switch group and a second signal for controlling ON/OFF of each switch of the second switch group.

公开(公告)号：US20220286123A1

公开(公告)日：2022-09-08

申请号：US17466322

申请日：2021-09-03

Applicant: NXP USA, Inc.

Inventor： Venkata Naga Koushik Malladi

IPC: H03K17/041 ,  H04B1/44

Abstract: Embodiments described herein include radio frequency (RF) switches that may provide increased power handling capability. In general, the embodiments described herein can provide this increased power handling by equalizing the voltages across transistors when the RF switch is open. Specifically, the embodiments described herein can be implemented to equalize the source-drain voltages across each field effect transistor (FET) in a FET stack that occurs when the RF switch is open and not conducting current. This equalization can be provided by using one or more compensation circuits to couple one or more gates and transistor bodies in the FET stack in a way that at least partially compensates for the effects of parasitic leakage currents in the FET stack. In addition, multiple FET stacks are implemented in parallel in at least some switch branches to improve settling time for the branch.

公开(公告)号：US20220037269A1

公开(公告)日：2022-02-03

申请号：US17371622

申请日：2021-07-09

Applicant: X-FAB Global Services GmbH

Inventor： Ralf LERNER ,  Nis Hauke HANSEN

IPC: H01L23/64 ,  H03K17/041

Abstract: The present invention suggests a semiconductor device for integration into a power module. The semiconductor device comprises (a) a semiconductor layer (10), a first side of the semiconductor layer (10) having a plurality of depressions (11); (b) an insulating layer (12; 12a, 12b), the insulating layer being deposited on the first side of the semiconductor layer (10) and engaging in the depressions (11); (c) a first electrically conductive layer (14; 14a, 14b) for contacting the semiconductor device (1, 2), the first electrically conductive layer (14; 14a, 14b) being deposited on the insulating layer (12a, 12b); and (d) a second electrically conductive layer (16) for contacting the semiconductor device (1, 2), the second electrically conductive layer (16) being deposited on a second side of the semiconductor layer (10) opposite to the first side. The first electrically conductive layer (14; 14a, 14b) has a plurality of recesses (20, 20) and a plurality of subregions (24), and each subregion (24) is enclosed by at least one recess (20), leaving at least one region (22, 22) having a narrowed cross-section.