公开(公告)号：US12237271B2

公开(公告)日：2025-02-25

申请号：US17488888

申请日：2021-09-29

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Tadashi Nomura ,  Toru Komatsu

IPC: H01L23/544 ,  H01L21/268 ,  H01L21/56 ,  H01L23/552 ,  H01L25/00

Abstract: A module is provided that includes a substrate having a first main surface, a component mounted on the first main surface, a first sealing resin disposed so as to cover the first main surface and the component, and a shield film covering at least an upper surface of the first sealing resin. The shield film includes a protective layer exposed to the outside and a conductive layer covered by the protective layer. The color of a surface of the conductive layer closer to the protective layer is different from the color of the protective layer. Moreover, the laser absorption coefficient of a material of the protective layer is higher than the laser absorption coefficient of a material forming the surface of the conductive layer closer to the protective layer. The module includes a marking section that is not covered by the protective layer and from which the conductive layer is exposed.

公开(公告)号：US12230585B2

公开(公告)日：2025-02-18

申请号：US18420972

申请日：2024-01-24

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Yeong-Jyh Lin ,  Ching I Li ,  De-Yang Chiou ,  Sz-Fan Chen ,  Han-Jui Hu ,  Ching-Hung Wang ,  Ru-Liang Lee ,  Chung-Yi Yu

IPC: H01L21/683 ,  G03F1/42 ,  G03F1/70 ,  H01L21/027 ,  H01L21/66 ,  H01L23/544

Abstract: Various embodiments of the present disclosure are directed towards a method for forming an integrated chip. An alignment process is performed on a first semiconductor workpiece and a second semiconductor workpiece by virtue of a plurality of workpiece pins. The first semiconductor workpiece is bonded to the second semiconductor workpiece. A shift value is determined between the first and second semiconductor workpieces by virtue of a first plurality of alignment marks on the first semiconductor workpiece and a second plurality of alignment marks on the second semiconductor workpiece. A layer of an integrated circuit (IC) structure is formed over the second semiconductor workpiece based at least in part on the shift value.

公开(公告)号：US20250054875A1

公开(公告)日：2025-02-13

申请号：US18680085

申请日：2024-05-31

Applicant: DENSO CORPORATION ,  TOYOTA JIDOSHA KABUSHIKI KAISHA ,  MIRISE Technologies Corporation

Inventor： MASASHI UECHA ,  YUJI NAGUMO ,  TAKAYA SHIMONO

IPC: H01L23/544 ,  H01L21/683 ,  H01L21/82 ,  H01L29/16 ,  H01L29/66

Abstract: A semiconductor device includes a semiconductor substrate having first and second main surfaces, first and second side surfaces opposite to each other in a first direction, and third and fourth side surfaces opposite to each other in a second direction perpendicular to the first direction, and a pattern structure disposed on the first main surface. The pattern structure within a first predetermined distance from the first side surface along the first direction and the pattern structure within the first predetermined distance from the second side surface along the first direction are symmetrical with respect to a line extending in the second direction. The pattern structure within a second predetermined distance from the third side surface along the second direction and the pattern structure within the second predetermined distance from the fourth side surface along the second direction are symmetrical with respect to a line extending in the first direction.

公开(公告)号：US12224207B2

公开(公告)日：2025-02-11

申请号：US16885526

申请日：2020-05-28

Applicant: DISCO Corporation

Inventor： Hitoshi Hoshino ,  Tzanimir Arguirov ,  Yasuyoshi Yubira ,  Karl Heinz Priewasser

IPC: H01L21/78 ,  H01L21/268 ,  H01L21/683 ,  H01L23/544

Abstract: The invention relates to a method of processing a workpiece having a first surface, a second surface opposite the first surface, and a third surface extending between the first and second surfaces. The method comprises forming modified regions inside the workpiece so as to create openings in the workpiece. The openings extend to at least one of the first surface, the second surface and the third surface. The method further comprises, after forming the modified regions inside the workpiece, introducing a liquid medium into at least some of the openings and, after introducing the liquid medium into the at least some of the openings, applying an external stimulus to the liquid medium so as to increase the volume of the medium. Moreover, the invention relates to a workpiece processing system for performing this method.

公开(公告)号：US20250046639A1

公开(公告)日：2025-02-06

申请号：US18720209

申请日：2021-12-17

Applicant: EV Group E. Thallner GmbH

Inventor： Thomas Wagenleitner ,  Harald Rohringer

IPC: H01L21/68 ,  H01L23/544

Abstract: The invention relates to a method and a device for the alignment of a substrate.

公开(公告)号：US20250046623A1

公开(公告)日：2025-02-06

申请号：US18919664

申请日：2024-10-18

Applicant: InnoLux Corporation

Inventor： Yeong-E CHEN ,  Cheng-En CHENG ,  Yu-Ting LIU ,  Cheng-Chi WANG

IPC: H01L21/48 ,  H01L21/66 ,  H01L21/683 ,  H01L23/544

Abstract: The application relates to a method for manufacturing an electronic device, and in particular, to a method for manufacturing an electronic device with a carrier substrate. The method includes: providing a carrier substrate; forming a first base layer on the carrier substrate; forming a working unit on the first base layer, performing a detection step on the working unit to identify whether a defect is present, wherein the detection step includes automated optical inspection (AOI), electrical detection, or a combination thereof; and repairing the electronic device.

公开(公告)号：US20250044350A1

公开(公告)日：2025-02-06

申请号：US18781351

申请日：2024-07-23

Applicant: MPI CORPORATION

Inventor： Andrej Rumiantsev ,  Lin-Lin CHIH ,  Ching-Ling PAI

IPC: G01R31/28 ,  G01R1/067 ,  H01L23/544

Abstract: A method of determining probing parameters for a probe system to test a DUT includes defining a SD-OD relation dataset according to the probe type of the probing assembly of the probe system and the contact pad type of the DUT, and providing the controller a skate distance value, for which the probe tip is set to skate after contacting the contact pad, or an overdrive value, for which the probing assembly and the DUT are set to be relatively moved after the probe tip contacts the contact pad, and a probe target position or a present probe position, to obtain both the skate distance value and the overdrive value and a position for positioning the probing assembly and the DUT to each other, thereby conveniently and quickly obtaining the required probing parameters for operating the probe system to test the DUT for great and consistent testing performance.

公开(公告)号：US12218073B2

公开(公告)日：2025-02-04

申请号：US17431756

申请日：2021-03-09

Applicant: CHANGXIN MEMORY TECHNOLOGIES, INC.

Inventor： Shengan Zhang

IPC: H01L23/544 ,  G01B11/00 ,  G03F7/00 ,  G03F7/20 ,  G03F9/00 ,  H01L21/68

Abstract: The present disclosure relates to a semiconductor mark and a forming method thereof. The semiconductor mark comprises: a previous layer mark comprising first patterns and at least one second pattern, the second pattern being located between adjacent first patterns, the first pattern being different from the second pattern in material property. Since the first pattern and the second pattern in the previous layer mark in the semiconductor mark according to the present disclosure are different in material property, during measurement, the first pattern and the second pattern are different in reflectivity for measurement light. Thus, the contrast of images of the first pattern and the second pattern obtained during measurement is improved, the positions and boundaries of the first pattern and the second pattern are clearly determined, and the measurement of the previous layer mark is more accurate.

公开(公告)号：US12217963B2

公开(公告)日：2025-02-04

申请号：US17594973

申请日：2020-04-27

Applicant: Tokyo Electron Limited

Inventor： Yutaka Yamasaki ,  Takashi Terada

IPC: H01L23/544 ,  B23K20/02 ,  B23K20/233 ,  B23K20/24 ,  H01L21/18 ,  H01L21/67

Abstract: A bonding apparatus configured to bond a first substrate and a second substrate includes: a first holder configured to hold the first substrate; a second holder disposed to face the first holder in a vertical direction, and configured to hold the second substrate; a processing vessel accommodating the first holder and the second holder therein; and a horizontal position adjuster provided outside the processing vessel and connected to the first holder via a support supporting the first holder, the horizontal position adjuster being configured to adjust a horizontal position of the first holder.

公开(公告)号：US20250038042A1

公开(公告)日：2025-01-30

申请号：US18916085

申请日：2024-10-15

Applicant: Amkor Technology Singapore Holding Pte. Ltd.

Inventor： Michael G. Kelly ,  Ronald Patrick Huemoeller ,  Won Chul Do ,  David Jon Hiner

IPC: H01L21/762 ,  H01L21/48 ,  H01L21/683 ,  H01L23/00 ,  H01L23/14 ,  H01L23/31 ,  H01L23/48 ,  H01L23/498 ,  H01L23/538 ,  H01L23/544 ,  H01L25/00

Abstract: Methods and systems for a semiconductor device package with a die to interposer wafer first bond are disclosed and may include bonding a plurality of semiconductor die comprising electronic devices to an interposer wafer, and applying an underfill material between the die and the interposer wafer. Methods and systems for a semiconductor device package with a die-to-packing substrate first bond are disclosed and may include bonding a first semiconductor die to a packaging substrate, applying an underfill material between the first semiconductor die and the packaging substrate, and bonding one or more additional die to the first semiconductor die. Methods and systems for a semiconductor device package with a die-to-die first bond are disclosed and may include bonding one or more semiconductor die comprising electronic devices to an interposer die.