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公开(公告)号：US20240186258A1
公开(公告)日：2024-06-06
申请号：US18420972
申请日：2024-01-24
Inventor： Yeong-Jyh Lin , Ching I Li , De-Yang Chiou , Sz-Fan Chen , Han-Jui Hu , Ching-Hung Wang , Ru-Liang Lee , Chung-Yi Yu
IPC: H01L23/544 , G03F1/42 , G03F1/70 , H01L21/027 , H01L21/66 , H01L21/683
CPC classification number: H01L23/544 , G03F1/42 , G03F1/70 , H01L21/0274 , H01L21/6835 , H01L22/20 , H01L2221/68309 , H01L2223/54426
Abstract: Various embodiments of the present disclosure are directed towards a method for forming an integrated chip. An alignment process is performed on a first semiconductor workpiece and a second semiconductor workpiece by virtue of a plurality of workpiece pins. The first semiconductor workpiece is bonded to the second semiconductor workpiece. A shift value is determined between the first and second semiconductor workpieces by virtue of a first plurality of alignment marks on the first semiconductor workpiece and a second plurality of alignment marks on the second semiconductor workpiece. A layer of an integrated circuit (IC) structure is formed over the second semiconductor workpiece based at least in part on the shift value.
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公开(公告)号：US20220328419A1
公开(公告)日：2022-10-13
申请号：US17834235
申请日：2022-06-07
Inventor： Yeong-Jyh Lin , Ching I. Li , De-Yang Chiou , Sz-Fan Chen , Han-Jui Hu , Ching-Hung Wang , Ru-Liang Lee , Chung-Yi Yu
IPC: H01L23/544 , H01L21/027 , H01L21/683 , G03F1/42 , G03F1/70 , H01L21/66
Abstract: Various embodiments of the present disclosure are directed towards a semiconductor processing system including an overlay (OVL) shift measurement device. The OVL shift measurement device is configured to determine an OVL shift between a first wafer and a second wafer, where the second wafer overlies the first wafer. A photolithography device is configured to perform one or more photolithography processes on the second wafer. A controller is configured to perform an alignment process on the photolithography device according to the determined OVL shift. The photolithography device performs the one or more photolithography processes based on the OVL shift.
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Patent Agency Ranking
公开(公告)号：US20230282612A1
公开(公告)日：2023-09-07
申请号：US18313492
申请日：2023-05-08
Inventor： Ching-Hung Wang , Yeong-Jyh Lin , Ching I Li , Tzu-Wei Yu , Chung-Yi Yu
CPC classification number: H01L24/83 , H01L21/681 , H01L24/98 , H01L2224/8393 , H01L2224/83136
Abstract: Various embodiments of the present disclosure are directed towards a method for forming a semiconductor structure. The method includes performing a bonding process to bond a first semiconductor substrate to a second semiconductor substrate. A shift measurement process is performed on the first and second semiconductor substrates. The shift measurement process includes moving a plurality of substrate pins from a plurality of initial positions to a plurality of measurement positions. The plurality of substrate pins are disposed outside of perimeters of the first and second semiconductor substrates. A shift value is determined between the first semiconductor substrate and the second semiconductor substrate based at least in part on a difference between the plurality of initial positions and the plurality of measurement positions.
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公开(公告)号：US12230585B2
公开(公告)日：2025-02-18
申请号：US18420972
申请日：2024-01-24
Inventor： Yeong-Jyh Lin , Ching I Li , De-Yang Chiou , Sz-Fan Chen , Han-Jui Hu , Ching-Hung Wang , Ru-Liang Lee , Chung-Yi Yu
IPC: H01L21/683 , G03F1/42 , G03F1/70 , H01L21/027 , H01L21/66 , H01L23/544
Abstract: Various embodiments of the present disclosure are directed towards a method for forming an integrated chip. An alignment process is performed on a first semiconductor workpiece and a second semiconductor workpiece by virtue of a plurality of workpiece pins. The first semiconductor workpiece is bonded to the second semiconductor workpiece. A shift value is determined between the first and second semiconductor workpieces by virtue of a first plurality of alignment marks on the first semiconductor workpiece and a second plurality of alignment marks on the second semiconductor workpiece. A layer of an integrated circuit (IC) structure is formed over the second semiconductor workpiece based at least in part on the shift value.
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公开(公告)号：US11916022B2
公开(公告)日：2024-02-27
申请号：US17834235
申请日：2022-06-07
Inventor： Yeong-Jyh Lin , Ching I Li , De-Yang Chiou , Sz-Fan Chen , Han-Jui Hu , Ching-Hung Wang , Ru-Liang Lee , Chung-Yi Yu
IPC: H01L23/544 , G03F1/42 , G03F1/70 , H01L21/027 , H01L21/66 , H01L21/683
CPC classification number: H01L23/544 , G03F1/42 , G03F1/70 , H01L21/0274 , H01L21/6835 , H01L22/20 , H01L2221/68309 , H01L2223/54426
Abstract: Various embodiments of the present disclosure are directed towards a semiconductor processing system including an overlay (OVL) shift measurement device. The OVL shift measurement device is configured to determine an OVL shift between a first wafer and a second wafer, where the second wafer overlies the first wafer. A photolithography device is configured to perform one or more photolithography processes on the second wafer. A controller is configured to perform an alignment process on the photolithography device according to the determined OVL shift. The photolithography device performs the one or more photolithography processes based on the OVL shift.
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公开(公告)号：US11688717B2
公开(公告)日：2023-06-27
申请号：US17412596
申请日：2021-08-26
Inventor： Ching-Hung Wang , Yeong-Jyh Lin , Ching I Li , Tzu-Wei Yu , Chung-Yi Yu
CPC classification number: H01L24/83 , H01L21/681 , H01L24/98 , H01L2224/8393 , H01L2224/83136
Abstract: Various embodiments of the present disclosure are directed towards a method for forming a semiconductor structure. The method includes loading a first wafer and a second wafer onto a bonding platform such that the second wafer overlies the first wafer. An alignment process is performed to align the second wafer over the first wafer by virtue of a plurality of wafer pins, where a plurality of first parameters are associated with the wafer pins during the alignment process. The second wafer is bonded to the first wafer. An overlay (OVL) measurement process is performed on the first wafer and the second wafer by virtue of the plurality of wafer pins, where a plurality of second parameters are associated with the wafer pins during the alignment process. An OVL shift is determined between the first wafer and the second wafer based on a comparison between the first parameters associated with the wafer pins during the alignment process and the second parameters associated with the wafer pins during the OVL measurement process.
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公开(公告)号：US20230066893A1
公开(公告)日：2023-03-02
申请号：US17412596
申请日：2021-08-26
Inventor： Ching-Hung Wang , Yeong-Jyh Lin , Ching I Li , Tzu-Wei Yu , Chung-Yi Yu
Abstract: Various embodiments of the present disclosure are directed towards a method for forming a semiconductor structure. The method includes loading a first wafer and a second wafer onto a bonding platform such that the second wafer overlies the first wafer. An alignment process is performed to align the second wafer over the first wafer by virtue of a plurality of wafer pins, where a plurality of first parameters are associated with the wafer pins during the alignment process. The second wafer is bonded to the first wafer. An overlay (OVL) measurement process is performed on the first wafer and the second wafer by virtue of the plurality of wafer pins, where a plurality of second parameters are associated with the wafer pins during the alignment process. An OVL shift is determined between the first wafer and the second wafer based on a comparison between the first parameters associated with the wafer pins during the alignment process and the second parameters associated with the wafer pins during the OVL measurement process.
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