Invention Grant
- Patent Title: Photolithography alignment process for bonded wafers
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Application No.: US17834235Application Date: 2022-06-07
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Publication No.: US11916022B2Publication Date: 2024-02-27
- Inventor: Yeong-Jyh Lin , Ching I Li , De-Yang Chiou , Sz-Fan Chen , Han-Jui Hu , Ching-Hung Wang , Ru-Liang Lee , Chung-Yi Yu
- Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicant Address: TW Hsin-Chu
- Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee Address: TW Hsinchu
- Agency: Eschweiler & Potashnik, LLC
- The original application number of the division: US17062677 2020.10.05
- Main IPC: H01L23/544
- IPC: H01L23/544 ; G03F1/42 ; G03F1/70 ; H01L21/027 ; H01L21/66 ; H01L21/683

Abstract:
Various embodiments of the present disclosure are directed towards a semiconductor processing system including an overlay (OVL) shift measurement device. The OVL shift measurement device is configured to determine an OVL shift between a first wafer and a second wafer, where the second wafer overlies the first wafer. A photolithography device is configured to perform one or more photolithography processes on the second wafer. A controller is configured to perform an alignment process on the photolithography device according to the determined OVL shift. The photolithography device performs the one or more photolithography processes based on the OVL shift.
Public/Granted literature
- US20220328419A1 PHOTOLITHOGRAPHY ALIGNMENT PROCESS FOR BONDED WAFERS Public/Granted day:2022-10-13
Information query
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