公开(公告)号：US20240363563A1

公开(公告)日：2024-10-31

申请号：US18766279

申请日：2024-07-08

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Hung-Shu Huang ,  Ming-Chyi Liu

IPC分类号： H01L23/00 ,  H01L23/31 ,  H01L23/495 ,  H01L23/498 ,  H01L23/532

CPC分类号： H01L24/05 ,  H01L23/3171 ,  H01L23/4952 ,  H01L23/49866 ,  H01L23/53295 ,  H01L24/03 ,  H01L2224/04042 ,  H01L2224/0558 ,  H01L2224/05686

摘要： A method includes depositing a first dielectric layer covering an electrical connector, depositing a second dielectric layer over the first dielectric layer, and performing a first etching process to etch-through the second dielectric layer and the first dielectric layer. An opening is formed in the first dielectric layer and the second dielectric layer to reveal the electrical connector. A second etching process is performed to laterally etch the first dielectric layer and the second dielectric layer. An isolation layer is deposited to extend into the opening. The isolation layer has a vertical portion and a first horizontal portion in the opening, and a second horizontal portion overlapping the second dielectric layer. An anisotropic etching process is performed on the isolation layer, with the vertical portion of the isolation layer being left in the opening.

公开(公告)号：US20240363533A1

公开(公告)日：2024-10-31

申请号：US18769153

申请日：2024-07-10

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Po-Hao TSAI ,  Techi WONG ,  Meng-Liang LIN ,  Yi-Wen WU ,  Po-Yao CHUANG ,  Shin-Puu JENG

IPC分类号： H01L23/528 ,  H01L23/00 ,  H01L23/31 ,  H01L23/495 ,  H01L23/498 ,  H01L23/538 ,  H01L25/00 ,  H01L25/065 ,  H01L25/07

CPC分类号： H01L23/5283 ,  H01L23/3128 ,  H01L23/3185 ,  H01L23/49575 ,  H01L23/49861 ,  H01L23/5389 ,  H01L24/09 ,  H01L24/17 ,  H01L24/32 ,  H01L25/0657 ,  H01L25/074 ,  H01L25/50 ,  H01L2224/0231 ,  H01L2224/02373 ,  H01L2224/02379 ,  H01L2224/02381 ,  H01L2224/0401 ,  H01L2224/3207 ,  H01L2224/32225 ,  H01L2225/06517 ,  H01L2225/0652 ,  H01L2924/1436 ,  H01L2924/1437

摘要： A package structure is provided. The package structure includes a first interconnect structure, a die structure over the first interconnect structure, and a dam structure on the die structure. The package structure also includes a second interconnect structure over the die structure and the dam structure. The package structure further includes a ring structure over the first interconnect structure and surrounding the die structure and the dam structure. In addition, the package structure includes a plurality of connectors electrically connected to the first interconnect structure and the second interconnect structure. A top surface of the ring structure is higher than a top surface of the first interconnect structure and lower than a top surface of each of the plurality of connectors.

公开(公告)号：US20240363499A1

公开(公告)日：2024-10-31

申请号：US18646482

申请日：2024-04-25

申请人： BRIDGE SEMICONDUCTOR CORP.

发明人： Charles W. C. LIN ,  Chia-Chung WANG

IPC分类号： H01L23/495 ,  H01L21/48 ,  H01L23/00

CPC分类号： H01L23/49558 ,  H01L21/4828 ,  H01L23/49548 ,  H01L24/16 ,  H01L24/48 ,  H01L23/4951 ,  H01L23/49513 ,  H01L23/49586 ,  H01L24/32 ,  H01L24/73 ,  H01L2224/16245 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48245 ,  H01L2224/73265

摘要： A lead frame substrate includes a circuitry layer, terminals, a warpage inhibiting dielectric layer and a stiffening dielectric layer. The circuitry layer extends laterally from the terminals and has an external surface facing away from the stiffening dielectric layer and an inner surface facing in and spaced from a top surface of the stiffening dielectric layer by the warpage inhibiting dielectric layer. The stiffening dielectric layer can serve as a robust platform to support the lateral extension of a circuitry layer and avoid crack propagation through the stiffening dielectric layer into the circuitry layer. The warpage inhibiting dielectric layer can absorb stress and alleviate warpage of the structure during bonding the stiffening dielectric layer to a lead frame with the terminals.

公开(公告)号：US20240363498A1

公开(公告)日：2024-10-31

申请号：US18307921

申请日：2023-04-27

申请人： Allegro MicroSystems, LLC

发明人： Maurizio Salato ,  William P. Taylor

IPC分类号： H01L23/495 ,  H01L21/56 ,  H01L23/31 ,  H01L25/16

CPC分类号： H01L23/49541 ,  H01L21/56 ,  H01L23/3107 ,  H01L25/16 ,  H01L28/10

摘要： Aspects of the present disclosure include systems, structures, circuits, and methods providing integrated circuit (IC) packages or modules having diagonalized leads. First and second semiconductor dies are disposed on a substrate. First and second coils are configured on the substrate for a transformer. The transformer may include a core. The leads or pins may be aligned along a diagonal of the package body, providing increased creepage. The IC packages and modules may include various types of circuits; in some examples, IC packages or modules may include a galvanically isolated gate driver or other high voltage circuit.

公开(公告)号：US20240363497A1

公开(公告)日：2024-10-31

申请号：US18641849

申请日：2024-04-22

申请人： Infineon Technologies AG

发明人： Andressa COLVERO SCHITTLER ,  Christian MÜLLER

IPC分类号： H01L23/495 ,  H01L23/00 ,  H01L25/065

CPC分类号： H01L23/49506 ,  H01L23/49575 ,  H01L24/08 ,  H01L24/48 ,  H01L25/0652 ,  H01L2224/08145 ,  H01L2224/08245 ,  H01L2224/48138 ,  H01L2224/48155 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/1306 ,  H01L2924/182

摘要： A semiconductor module arrangement includes a substrate including a dielectric insulation layer and a first metallization layer arranged on a surface of the dielectric insulation layer, wherein the first metallization layer comprises a first section, a second section, and a third section, and a first semiconductor body and an identical second semiconductor body arranged on the first metallization layer, wherein each of the first semiconductor body and the second semiconductor body has a first contact pad, a second contact pad, and a third contact pad arranged on a top side of the respective semiconductor body that faces away from the substrate, wherein the third contact pad of the first semiconductor body is electrically coupled to the third section of the first metallization layer by means of a first electrical connection element, the third contact pad of the second semiconductor body is electrically coupled to the third section of the first metallization layer by means of a second electrical connection element, the semiconductor module arrangement further includes at least one third terminal element arranged on the third section, a first current path between the third contact pad of the first semiconductor body and the at least one third terminal element provides identical voltage and current transfer characteristics as a second current path between the third contact pad of the second semiconductor body and the at least one third terminal element, and each of the first and second electrical connection elements includes one or more bonding wires, one or more bonding ribbons, a connection rail, or a section of an additional metallization layer of the substrate that is contacted by corresponding vias.

公开(公告)号：US20240363465A1

公开(公告)日：2024-10-31

申请号：US18309546

申请日：2023-04-28

申请人： Texas Instruments Incorporated

发明人： Anindya Poddar ,  Daiki Komatsu ,  Hau Nguyen

IPC分类号： H01L23/31 ,  H01L21/56 ,  H01L21/78 ,  H01L23/00 ,  H01L23/495

CPC分类号： H01L23/3135 ,  H01L21/561 ,  H01L21/78 ,  H01L23/49513 ,  H01L24/05 ,  H01L24/32 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/92 ,  H01L21/568 ,  H01L23/291 ,  H01L23/293 ,  H01L2224/05558 ,  H01L2224/05686 ,  H01L2224/0569 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48108 ,  H01L2224/48245 ,  H01L2224/49173 ,  H01L2224/73265 ,  H01L2224/92247 ,  H01L2924/05442 ,  H01L2924/0695 ,  H01L2924/07025

摘要： An electronic device includes a semiconductor die, a die attach pad, an adhesive, a conductive lead, and a package structure, where the semiconductor die has opposite first and second sides, a conductive terminal on the second side, and an electrical isolation coating layer that extends on the first side, the adhesive adheres the first side of the semiconductor die to the die attach pad, the conductive lead is electrically coupled to the conductive terminal of the semiconductor die, and the package structure encloses at least a portion of the semiconductor die.

公开(公告)号：US20240355753A1

公开(公告)日：2024-10-24

申请号：US18553211

申请日：2022-02-25

申请人： PIERBURG GMBH

发明人： MIKA NUOTIO ,  DIETER JELINEK ,  OGUZ DEMIR ,  PATRICK BAUER

IPC分类号： H01L23/538 ,  H01L23/00 ,  H01L23/36 ,  H01L23/495 ,  H01L25/16

CPC分类号： H01L23/5386 ,  H01L23/5385 ,  H01L25/162 ,  H01L23/36 ,  H01L23/49517 ,  H01L24/48 ,  H01L2224/48137 ,  H01L2224/48225

摘要： A power semiconductor package includes a first substrate assembly with power semiconductor dies, a second substrate assembly arranged parallel to the first substrate assembly, and source contacts. The second substrate assembly has a copper cladding layer which defines a source copper cladding layer circuit having a bonding area which, when mechanically contacted, provides an electrical connection to the source copper cladding layer circuit. Each of the source contacts provide an electrical connection between a source connection of one of the power semiconductor dies and the source copper cladding layer circuit. The source contacts are arranged at different distances from the bonding area of the source copper cladding layer circuit. The source copper cladding layer circuit also has an electrically isolating slot arranged between one of the source contacts which is closest to the bonding area of the source copper cladding layer circuit and the bonding area.

公开(公告)号：US20240355638A1

公开(公告)日：2024-10-24

申请号：US18760515

申请日：2024-07-01

申请人： SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

发明人： Yong LIU ,  Yusheng LIN ,  Liangbiao CHEN

IPC分类号： H01L21/48 ,  H01L21/56 ,  H01L23/28 ,  H01L23/495 ,  H01L23/498

CPC分类号： H01L21/4821 ,  H01L21/56 ,  H01L23/28 ,  H01L23/49534 ,  H01L23/49575 ,  H01L23/49582 ,  H01L23/498 ,  H01L23/49822 ,  H01L23/49861

摘要： Methods of forming semiconductor packages include providing a first insulator layer coupled with a first metallic layer. A recess is formed in the first metallic layer and a semiconductor die is mechanically coupled therein. The die is mechanically coupled with a second metallic layer and the second metallic layer is coupled with a second insulator layer. The die and layers are at least partially encapsulated to form the semiconductor package. The first and/or second metallic layers may be insulator-metal substrates, metal-insulator-metal (MIM) substrates, or may be formed of lead frames. In implementations the package does not include a spacer between the die and the first metallic layer and does not include a spacer between the die and the second metallic layer. In implementations the first insulator layer and the second insulator layer are exposed through the encapsulant or are mechanically coupled with metallic layers exposed through the encapsulant.

公开(公告)号：US12125774B2

公开(公告)日：2024-10-22

申请号：US17738342

申请日：2022-05-06

申请人： SUMITOMO ELECTRIC DEVICE INNOVATIONS, INC

发明人： Hisashi Shimura ,  Yoshiyasu Kuwabara

IPC分类号： H01L23/495 ,  H01L21/56 ,  H01L23/31 ,  H01L29/267 ,  H01L29/78

CPC分类号： H01L23/49562 ,  H01L21/561 ,  H01L23/3121 ,  H01L23/49582 ,  H01L29/267 ,  H01L29/78

摘要： A semiconductor device includes a semiconductor chip in which a field effect transistor mainly containing GaN is formed on a surface of a SiC semiconductor substrate. The semiconductor device includes a metal base on which a back surface of the semiconductor chip is mounted through a conductive adhesive material containing Ag and a resin mold configured to seal the semiconductor chip. A metal having wettability lower than wettability of Au or Cu with respect to Ag is exposed in a region extending along an edge of the back surface.

公开(公告)号：US12125770B2

公开(公告)日：2024-10-22

申请号：US17287504

申请日：2019-07-19

申请人： Shenzhenshi Pengyuan Electronics Co., Ltd.

发明人： Chunxian Ye ,  Xubiao Zhan ,  Tao Li ,  Shengchao Ruan

IPC分类号： H02M7/00 ,  H01L23/31 ,  H01L23/49 ,  H01L23/495 ,  H02K11/33

CPC分类号： H01L23/49 ,  H01L23/3107 ,  H01L23/49503 ,  H02K11/33 ,  H02M7/003

摘要： An in-line power device, a semiconductor assembly, an in-wheel motor driver or a vehicle driver, and a new-energy vehicle are provided. The in-line power device includes: a body including a power chip and a wrapping layer wrapping an outer surface of the power chip; and a plurality of pins provided at a first side of the body at intervals. The plurality of pins includes a power pin, an auxiliary control pin and a control signal pin, and each pin includes a first segment provided inside the wrapping layer and a second segment provided outside the wrapping layer. The second segment of the auxiliary control pin and the second segment of the control signal pin are located in a first plane, the second segment of the power pin and the first side are located in a second plane, and the first plane is not parallel to the second plane.