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    POWER SEMICONDUCTOR MODULE ARRANGEMENT AND METHOD FOR PRODUCING THE SAME
    3.
    发明申请
    POWER SEMICONDUCTOR MODULE ARRANGEMENT AND METHOD FOR PRODUCING THE SAME 有权

    公开(公告)号：US20250062137A1

    公开(公告)日：2025-02-20

    申请号：US18797564

    申请日：2024-08-08

    Applicant: Infineon Technologies AG

    Inventor： Markus Wiesemann ,  Anita Herzer

    IPC: H01L21/56 ,  H01L23/29 ,  H01L23/31

    Abstract: A method includes: filling a first material having a first density in a housing to form a liquid or gel-like first pre-layer, the housing having sidewalls, and a substrate with at least one semiconductor body arranged thereon is arranged in or forms a ground surface of the housing, the first pre-layer partly filling the housing and completely covering the substrate and the at least one semiconductor body; filling a second material being different from the first material and having a second density in the housing, the first density being higher than the second density, to form a liquid or gel-like second pre-layer, the first pre-layer forming between the second pre-layer and the substrate; and performing a curing step that simultaneously cures the first material and the second material and forms a solid first layer and a solid second layer, the second layer permanently adhering to the first layer.

    Type III-V semiconductor device with structured passivation
    4.
    发明授权
    Type III-V semiconductor device with structured passivation 有权

    公开(公告)号：US12230700B2

    公开(公告)日：2025-02-18

    申请号：US17667927

    申请日：2022-02-09

    Applicant: Infineon Technologies Austria AG

    Inventor： Simone Lavanga ,  Nicholas Dellas ,  Gerhard Prechtl ,  Luca Sayadi

    IPC: H01L29/778 ,  H01L21/02 ,  H01L21/76 ,  H01L21/765 ,  H01L23/29 ,  H01L23/31 ,  H01L29/20 ,  H01L29/205 ,  H01L29/40 ,  H01L29/66

    Abstract: A high-electron-mobility transistor comprises a semiconductor body comprising a barrier region and a channel region that forms a heterojunction with the barrier region such that a two-dimensional charge carrier gas channel is disposed in the channel region, source and drain electrodes disposed on the semiconductor body and laterally spaced apart from one another, a gate structure disposed on the semiconductor body and laterally between the source and drain electrodes, the gate structure being configured to control a conduction state of two-dimensional charge carrier gas, and a first dielectric region that is disposed along the upper surface of the semiconductor body in a lateral region that is between the gate structure and the drain electrode, wherein the first dielectric region comprises aluminum and oxide, and wherein first dielectric region comprises a first end that faces and is laterally spaced apart from the gate structure.

    Substrate-free semiconductor device assemblies with multiple semiconductor devices and methods for making the same
    8.
    发明授权
    Substrate-free semiconductor device assemblies with multiple semiconductor devices and methods for making the same 有权

    公开(公告)号：US12211798B1

    公开(公告)日：2025-01-28

    申请号：US18218589

    申请日：2023-07-06

    Applicant: Micron Technology, Inc.

    Inventor： Hung Wen Liu

    IPC: H01L23/538 ,  H01L21/768 ,  H01L23/29

    Abstract: A semiconductor device assembly includes a first remote distribution layer (RDL), the first RDL comprising a lower outermost planar surface of the semiconductor device assembly; a first semiconductor die directly coupled to an upper surface of the first RDL by a first plurality of interconnects; a second RDL, the second RDL comprising an upper outermost planar surface of the semiconductor device assembly opposite the lower outermost planar surface; a second semiconductor die directly coupled to a lower surface of the second RDL by a second plurality of interconnects; an encapsulant material disposed between the first RDL and the second RDL and at least partially encapsulating the first and second semiconductor dies; and a third plurality of interconnects extending fully between and directly coupling the upper surface of the first RDL and the lower surface of the second RDL.

    SEMICONDUCTOR MODULE AND METHOD FOR MANUFACTURING SEMICONDUCTOR MODULE
    9.
    发明申请
    SEMICONDUCTOR MODULE AND METHOD FOR MANUFACTURING SEMICONDUCTOR MODULE 有权

    公开(公告)号：US20250029883A1

    公开(公告)日：2025-01-23

    申请号：US18673318

    申请日：2024-05-24

    Applicant: FUJI ELECTRIC CO., LTD.

    Inventor： Shohei KASAI

    IPC: H01L23/31 ,  H01L23/00 ,  H01L23/29 ,  H01L23/498

    Abstract: Providing a semiconductor module, including: a laminated substrate; multiple semiconductor chips provided on the laminated substrate; a bonding wire connected to the multiple semiconductor chips; a housing which accommodates the multiple semiconductor chips, the bonding wire, and the laminated substrate; a first encapsulation layer which covers the multiple semiconductor chips, the bonding wire, and the laminated substrate inside the housing; a second encapsulation layer provided on the first encapsulation layer; and a third encapsulation layer provided on the second encapsulation layer. The first encapsulation layer is filled inside the housing up to a position higher than an upper surface of the bonding wire, and hardness of the second encapsulation layer is greater than hardness of the first encapsulation layer and less than hardness of the third encapsulation layer.

    Semiconductor Device and Methods of Manufacture
    10.
    发明申请
    Semiconductor Device and Methods of Manufacture 有权

    公开(公告)号：US20250022763A1

    公开(公告)日：2025-01-16

    申请号：US18352363

    申请日：2023-07-14

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Sheng-Han Tsai ,  Tsung-Yu Chen ,  Hong-Yu Guo ,  Tsung-Shu Lin

    IPC: H01L23/31 ,  H01L21/56 ,  H01L21/683 ,  H01L23/00 ,  H01L23/29 ,  H01L25/10

    Abstract: Semiconductor device and methods of manufacture are provided. In an embodiment, the a semiconductor device may include a first semiconductor die; an oxide layer on the first semiconductor die, wherein the first semiconductor die has a first top surface opposite the oxide layer; a first insulating material encapsulating the first semiconductor die and the oxide layer, wherein the first insulating material has a second top surface planar with the first top surface; and a first polymer buffer disposed between a sidewall of the first semiconductor die and a sidewall of the oxide layer, wherein the first polymer buffer has a third top surface planar with both the first top surface and the second top surface.

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