公开(公告)号：US20250053512A1

公开(公告)日：2025-02-13

申请号：US18777466

申请日：2024-07-18

Applicant: Micron Technology, Inc.

Inventor： Robert M. Walker

IPC: G06F12/06

Abstract: Mapping addresses to banks can include receiving a plurality of row bits, a plurality of column bits, and a plurality of bank bits and generating a rank bit from a bank bit from the plurality of bank bits. Updated bank bits can be generated by removing the bank bit from the plurality of bank bits. The plurality of row bits, the plurality of column bits, the rank bit, and the updated bank bits can be provided to the controller to access a plurality of banks of the memory device.

公开(公告)号：US12223347B2

公开(公告)日：2025-02-11

申请号：US17333449

申请日：2021-05-28

Applicant: Microsoft Technology Licensing, LLC

Inventor： Marsh Jordan Ray

IPC: G06F9/455 ,  G06F9/48 ,  G06F12/06 ,  G06F21/56

Abstract: Aspects of the present disclosure relate to volatile memory acquisition using live migration of an execution environment. In examples, a virtualization manager controls execution of an execution environment at a virtualization host. The virtualization manager may enable live migration of the execution environment, such that the execution environment may be migrated to another virtualization host (or “migration target”) for continued execution. Accordingly, such functionality may be used to capture a memory image at a migration target, after which the execution environment continues executing at the original virtualization host. The memory image may be analyzed to identify the presence of malware and/or to generate a list of processes that were executing at the time of the capture. Such aspects may enable capturing a substantially accurate and consistent memory image of the volatile memory of the execution environment without indicating, inadvertently or otherwise, that a capture is occurring to processes executing therein.

公开(公告)号：US12216573B2

公开(公告)日：2025-02-04

申请号：US18395363

申请日：2023-12-22

Applicant: Micron Technology, Inc.

Inventor： Kishore Kumar Muchherla ,  Peter Feeley ,  Ashutosh Malshe ,  Daniel J. Hubbard ,  Christopher S. Hale ,  Kevin R. Brandt ,  Sampath K. Ratnam ,  Yun Li ,  Marc S. Hamilton

IPC: G06F3/00 ,  G06F3/06 ,  G06F12/00 ,  G06F12/02 ,  G06F12/06 ,  G06F12/0891 ,  G11C11/56

Abstract: A memory system includes a memory array having a plurality of memory cells; and a controller coupled to the memory array, the controller configured to: designate a storage mode for a target set of memory cells based on valid data in a source block, wherein the target set of memory cells are configured with a capacity to store up to a maximum number of bits per cell, and the storage mode is for dynamically configuring the target set of memory cells in as cache memory that stores a number of bits less per cell than the corresponding maximum capacity.

公开(公告)号：US20250036579A1

公开(公告)日：2025-01-30

申请号：US18625212

申请日：2024-04-03

Applicant: Micron Technology, Inc.

Inventor： Raymond Chang ,  Raghukiran Sreeramaneni ,  Nevil N. Gajera

IPC: G06F13/16 ,  G06F12/06

Abstract: A memory device (e.g., a high-bandwidth memory (HBM) device) with multiple physical interfaces (PHYs) is disclosed. The memory device includes a base semiconductor die having a first physical interface (PHY) arranged in accordance with a Joint Electron Device Engineering Council (JEDEC) standard and a second PHY arranged differently from the first PHY and electrically disconnected from the first PHY. The base semiconductor die further includes first contacts disposed at a first side of the base semiconductor die and second contacts disposed at a second side of the base semiconductor die opposite the first side. The first contacts and the second contacts couple with a first one of the first PHY and the second PHY. The memory device further includes one or more memory dies coupled with the base semiconductor die through the second contacts.

公开(公告)号：US12210470B2

公开(公告)日：2025-01-28

申请号：US17730174

申请日：2022-04-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Oscar P. Pinto ,  William Martin

IPC: G06F13/38 ,  G06F9/50 ,  G06F9/54 ,  G06F12/06 ,  G06F13/14

Abstract: A method may include interacting with an interface for one or more computational devices, wherein the interacting is based on an identifier, and wherein the identifier comprises information that identifies a functionality of a computational device functions. The information may include a functionality identifier. The identifier may further include information that identifies a group of the computational device function. The group of the computational device function may be based on a source of the computational device function. The information that identifies the functionality of a computational device function may include a functionality identifier, and the information that identifies the group of the computational device function may include a group identifier. The functionality identifier may include a unique function identifier, and the group identifier may include an organizationally unique identifier.

公开(公告)号：US20250028636A1

公开(公告)日：2025-01-23

申请号：US18794937

申请日：2024-08-05

Applicant: Rambus Inc.

Inventor： Taeksang SONG ,  Steven C. WOO ,  Torsten PARTSCH

IPC: G06F12/06 ,  G11C11/408

Abstract: Row addresses received by a module are mapped before being received by the memory devices of the module such that row hammer affects different neighboring row addresses in each memory device. Thus, because the mapped respective, externally received, row addresses applied to each device ensure that each set of neighboring rows for a given row address received by the module is different for each memory device on the module, row hammering of a given externally addressed row spreads the row hammering errors across different externally addressed rows on each memory device. This has the effect of confining the row hammer errors for each row that is hammered to a single memory device per externally addressed neighboring row. By confining the row hammer errors to a single memory device, the row hammer errors are correctible using a SDDC scheme.

公开(公告)号：US12204447B2

公开(公告)日：2025-01-21

申请号：US17943119

申请日：2022-09-12

Applicant: MemryX Incorporated

Inventor： Mohammed Zidan ,  Jacob Botimer ,  Timothy Wesley ,  Chester Liu ,  Wei Lu

IPC: G06F3/06 ,  G06F9/46 ,  G06F12/02 ,  G06F12/06 ,  G06N3/045 ,  G06N3/063 ,  G11C11/54

Abstract: A memory processing unit (MPU) configuration method can include mapping operations of one or more neural network models to sets of cores in a plurality of processing regions. In addition, dataflow of the one or more neural network models can be mapped to the sets of cores in the plurality of processing regions. Furthermore, configuration information can be generated based on the mapping of the operations of the one or more neural network models to the set of cores in the plurality of processing regions and the mapping of dataflow of the one or more neural network models to the sets of cores in the plurality of processing regions. The method can be implemented by generating an initial graph from a neural network model. A mapping graph can then be generated from the final graph. One or more configuration files can then be generated from the mapping graph.

公开(公告)号：US20250021342A1

公开(公告)日：2025-01-16

申请号：US18896712

申请日：2024-09-25

Applicant: Oracle International Corporation

Inventor： Mario Wolczko

IPC: G06F9/445 ,  G06F12/06

Abstract: A processor may implement self-relative memory addressing by providing load and store instructions that include self-relative addressing modes. A memory address may contain a self-relative pointer, where the memory address stores a memory offset that, when added to the memory address, defines another memory address. The self-relative addressing mode may also support invalid memory addresses using a reserved offset value, where a load instruction providing the self-relative addressing mode may return a NULL value or generate an exception when determining that the stored offset value is equal to the reserved offset value and where a store instruction providing the self-relative addressing mode may store the reserved offset value when determining that the pointer is an invalid or NULL memory address.

公开(公告)号：US12197328B2

公开(公告)日：2025-01-14

申请号：US18220765

申请日：2023-07-11

Applicant: Neo4j Sweden AB

Inventor： Anton Klarén

IPC: G06F12/06 ,  G06F16/21 ,  G06F16/23

Abstract: Techniques are disclosed to manage use of a global pool of memory comprising at least a portion of the runtime-managed heap. A request to reserve use of a portion of the global pool of memory is received from each of a plurality of transactions comprising a transactional workload of a database management system. A corresponding portion of the global pool of memory is allocated to each of at least a subset of the requesting transactions, to be used as a local pool of memory available to be used by the transaction to process the transaction.

公开(公告)号：US12197327B2

公开(公告)日：2025-01-14

申请号：US18338797

申请日：2023-06-21

Applicant: SK hynix Inc.

Inventor： Dae Sung Kim ,  Bi Woong Chung

IPC: G06F12/06

Abstract: A decoding device may determine a candidate data unit among a plurality of data units included in one data chunk, in parallel with an operation of decoding a target data unit among the plurality of data units. The decoding device may determine whether to decode the candidate data unit, and may decode the candidate data unit according to whether to decode the candidate data unit, after executing decoding on the target data unit.