公开(公告)号：US20230075069A1

公开(公告)日：2023-03-09

申请号：US17943100

申请日：2022-09-12

Applicant: MemryX Incorporated

Inventor： Mohammed Zidan ,  Jacob Botimer ,  Timothy Wesley ,  Chester Liu ,  Zhengya Zhang ,  Wei Lu

IPC: G06F3/06

Abstract: A memory processing unit (MPU) can include a first memory, a second memory, a plurality of processing regions and control logic. The first memory can include a plurality of regions. The plurality of processing regions can be interleaved between the plurality of regions of the first memory. The processing regions can include a plurality of compute cores. The second memory can be coupled to the plurality of processing regions. The control logic can configure data flow between compute cores of one or more of the processing regions and corresponding adjacent regions of the first memory. The control logic can also configure data flow between the second memory and the compute cores of one or more of the processing regions. The control logic can also configure data flow between compute cores within one or more respective ones of the processing regions.

公开(公告)号：US12204447B2

公开(公告)日：2025-01-21

申请号：US17943119

申请日：2022-09-12

Applicant: MemryX Incorporated

Inventor： Mohammed Zidan ,  Jacob Botimer ,  Timothy Wesley ,  Chester Liu ,  Wei Lu

IPC: G06F3/06 ,  G06F9/46 ,  G06F12/02 ,  G06F12/06 ,  G06N3/045 ,  G06N3/063 ,  G11C11/54

Abstract: A memory processing unit (MPU) configuration method can include mapping operations of one or more neural network models to sets of cores in a plurality of processing regions. In addition, dataflow of the one or more neural network models can be mapped to the sets of cores in the plurality of processing regions. Furthermore, configuration information can be generated based on the mapping of the operations of the one or more neural network models to the set of cores in the plurality of processing regions and the mapping of dataflow of the one or more neural network models to the sets of cores in the plurality of processing regions. The method can be implemented by generating an initial graph from a neural network model. A mapping graph can then be generated from the final graph. One or more configuration files can then be generated from the mapping graph.

公开(公告)号：US20230073012A1

公开(公告)日：2023-03-09

申请号：US17943116

申请日：2022-09-12

Applicant: MemryX Incorporated

Inventor： Jacob Botimer ,  Mohammed Zidan ,  Timothy Wesley ,  Chester Liu ,  Wei Lu

IPC: G06F12/06 ,  G06F12/02

Abstract: A memory processing unit (MPU) can include a first memory, a second memory, a plurality of processing regions and control logic. The first memory can include a plurality of regions. The plurality of processing regions can be interleaved between the plurality of regions of the first memory. The processing regions can include a plurality of compute cores. The second memory can be coupled to the plurality of processing regions. The control logic can configure data flow between compute cores of one or more of the processing regions and corresponding adjacent regions of the first memory. The control logic can also configure data flow between the second memory and the compute cores of one or more of the processing regions. The control logic can also configure data flow between compute cores within one or more respective ones of the processing regions. The control logic can also configure array data for storage memory of the MPU.

公开(公告)号：US20230072556A1

公开(公告)日：2023-03-09

申请号：US17944014

申请日：2022-09-13

Applicant: MemryX Incorporated

Inventor： Zih-Sing Fu ,  Wen-Cong Huang ,  Chia-Hsiang Yang ,  Zhengya Zhang ,  Timothy Wesley ,  Jacob Botimer

IPC: G06F3/06

Abstract: A computing system can include an off-chip memory and processing unit integrated circuitry. The processing unit IC can include on-chip compute circuitry, a first on-chip memory and a second on-chip memory. The off-chip memory can be configured to store instructions and data The first on-chip memory can be configured to store reusable portions of the instructions and or data for use by the on-chip compute circuitry. The second on-chip memory configured to cache portions of instruction and data for current use by the on-chip compute circuitry.