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    Integrated Impedance Measurement Device and Impedance Measurement Method Thereof
    2.
    发明公开
    Integrated Impedance Measurement Device and Impedance Measurement Method Thereof 审中-公开

    公开(公告)号：US20240345146A1

    公开(公告)日：2024-10-17

    申请号：US18753371

    申请日：2024-06-25

    申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

    发明人： Haohua Zhou ,  Mei Hsu Wong ,  Tze-Chiang Huang

    IPC分类号： G01R27/16 ,  G01R31/30 ,  G01R31/319

    CPC分类号： G01R27/16 ,  G01R31/30 ,  G01R31/31905

    摘要： Systems, devices, and methods are described herein for measuring an impedance of a DUT using an integrated impedance measurement device. A system includes a plurality of measurement circuits, a FFT processor, and a controller. The measurement circuits are coupled to the DUTs. Each measurement circuit is configured to generate a clock signal for a respective DUT, detect a voltage of the respective DUT, and generate first voltage related data using the clock signal and the voltage. The FFT processor is coupled to the measurement circuits. The FFT processor is configured to convert the first voltage related data into second voltage related data using a fast Fourier transform for each measurement circuit. The controller is coupled to the measurement circuits and the FFT processor. The controller is configured to calculate an impedance using the second voltage related data for each measurement circuit and output the impedance to each DUT.

    Virtual machine testing of electrical machines using physical domain performance signatures
    3.
    发明授权
    Virtual machine testing of electrical machines using physical domain performance signatures 有权

    公开(公告)号：US12117482B2

    公开(公告)日：2024-10-15

    申请号：US17921136

    申请日：2021-04-28

    申请人： Vestas Wind Systems A/S

    发明人： Peter Mongeau

    IPC分类号： G01R31/28 ,  G01R31/319

    CPC分类号： G01R31/2872 ,  G01R31/31917

    摘要： Systems, methods, and computer program products for virtual machine testing of an electric machine. A test signature including parameter values measured during one or more static tests of the electric machine is compared to a reference signature generated by performing a similar series of static tests on a reference machine. The reference machine is then validated by subjecting the reference machine to full-load dynamic testing. The test and reference signatures may include a plurality of parameters each characterizing a physical property of the respective machines in one or more physical domains. The parameters are selected so that the electric machine can be qualified for operation in the field by comparing the test signature to the reference signature, thereby avoiding the need for full-load dynamic testing of the electric machine.

    TEST CIRCUIT AND TEST APPARATUS COMPRISING THE TEST CIRCUIT
    4.
    发明公开
    TEST CIRCUIT AND TEST APPARATUS COMPRISING THE TEST CIRCUIT 审中-公开

    公开(公告)号：US20240337694A1

    公开(公告)日：2024-10-10

    申请号：US18311870

    申请日：2023-05-03

    申请人： Montage Technology Co., Ltd.

    发明人： Dongming LOU ,  Weidong FAN ,  Zhongyuan Chang

    IPC分类号： G01R31/319 ,  G01R31/28

    CPC分类号： G01R31/31905 ,  G01R31/2879 ,  G01R31/31924 ,  G01R27/14

    摘要： A test circuit includes a signal processor, a first resistor, a second resistor, a first switch, and a second switch. The signal processor is coupled to a first drive end, a second drive end, a first sensing end, and a second sensing end. The first resistor is coupled between the first drive end and the first sensing end. The second resistor is coupled between the second drive end and the second sensing end. The first switch is coupled between the first sensing end and a first end of a device under test. The second switch is coupled between the second sensing end and a second end of the device under test. The first drive end is coupled to the first end of the device through a first transmission wire, and the second drive end is coupled to the second end of the device through a second transmission wire.

    Test devices, test systems, and operating methods of test systems
    5.
    发明授权
    Test devices, test systems, and operating methods of test systems 有权

    公开(公告)号：US12111351B2

    公开(公告)日：2024-10-08

    申请号：US17522188

    申请日：2021-11-09

    申请人： Samsung Electronics Co., Ltd.

    发明人： Ungjin Jang ,  Seonggwon Jang ,  Yongjeong Kim ,  Sooyong Park

    IPC分类号： G11C29/56 ,  G01R31/317 ,  G01R31/319 ,  G11C29/08

    CPC分类号： G01R31/31702 ,  G01R31/31905 ,  G11C29/08 ,  G11C29/56 ,  G11C2029/5602

    摘要： A test device configured to test a device under test (DUT) performing an interface of a pulse amplitude modulation (PAM) operation includes a logic generation/determination device configured to generate multiple bits corresponding to a test pattern, first and second drivers configured to generate respective first and second non return to zero (NRZ) signals according to a logic state of respective first and second bits among the multiple bits and output the respective generated first and second NRZ signals via respective first and second channels. The first NRZ signal has a first high level or a first low level according to the logic state of the first bit, and the second NRZ signal has a second high level or a second low level according to the logic state of the second bit. The first and second high levels are different from each other.

    CLOCK RECOVERY UNIT ADJUSTMENT
    7.
    发明公开
    CLOCK RECOVERY UNIT ADJUSTMENT 审中-公开

    公开(公告)号：US20240243896A1

    公开(公告)日：2024-07-18

    申请号：US18097047

    申请日：2023-01-13

    申请人： Keysight Technologies, Inc.

    发明人： Marlin E. Viss ,  Mark Joseph Woodward

    IPC分类号： G01R31/317 ,  G01R31/319 ,  H03L7/08

    CPC分类号： G01R31/31727 ,  G01R31/31919 ,  H03L7/0807

    摘要： A controller includes a memory, a processor, and a first interface to a clock recovery unit that provides a recovered clock. When executed by the processor, instructions from the memory cause the controller to: instruct, via the first interface, the clock recovery unit at a first loop bandwidth to provide the recovered clock to a signal sampler; instruct, via the first interface, the clock recovery unit at a second loop bandwidth wider than the first loop bandwidth, to provide the recovered clock to the signal sampler; compare measurements from the signal sampler at the first loop bandwidth to measurements from the signal sampler at the second loop bandwidth; and instruct, via the first interface, the clock recovery unit at a third loop bandwidth to provide the recovered clock to the signal sampler applying adjustments based on comparing the measurements.

    Method for semiconductor device interface circuitry functionality and compliance testing
    10.
    发明授权
    Method for semiconductor device interface circuitry functionality and compliance testing 有权

    公开(公告)号：US12025663B2

    公开(公告)日：2024-07-02

    申请号：US17122202

    申请日：2020-12-15

    申请人： CELERINT, LLC

    发明人： Howard H. Roberts, Jr. ,  LeRoy Growt ,  Thomas Schoen

    IPC分类号： G01R31/319 ,  G01R31/3183

    CPC分类号： G01R31/31924 ,  G01R31/31835 ,  G01R31/31905 ,  G01R31/31926

    摘要： A method is provided for testing the functionality of a device under test interface circuitry located between automated testing equipment (ATE) and a device under test (DUT). The method includes disconnecting the device under test from the device under test interface circuitry, utilizing a Source Measurement Unit (SMU) that generates and measures voltage and current and uses force and sense lines, and testing a switch located in the device under test interface circuitry using a two-state alarm process. The method also includes applying a voltage using the a voltage source measurement device in a first state in which force and sense lines of the voltage source measurement device are connected in the device under test interface circuitry. The method further includes detecting whether an alarm signal due to an open circuit has been activated, and determining that the switch being tested in the device under test interface circuitry is operating properly by the absence of the alarm signal being activated.