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公开(公告)号：US4570121A
公开(公告)日：1986-02-11
申请号：US504900
申请日：1983-06-16
申请人： Robert L. Carbrey
发明人： Robert L. Carbrey
CPC分类号： H03M1/44
摘要： An analog-to-digital converter circuit is disclosed employing a plurality of comparators each having the same reference voltage input. At each comparator stage plus and minus binary "bit weights" are developed. Selection of either the positive or negative bit weights at a stage allows a binary fraction to be added or subtracted. The number of comparator stages need only equal the number of desired digit positions in the output instead of having one comparator for each quantizing level. The comparator stages operate in a "wave" or "pipeline" manner under the control of a plurality of high speed wave forms so that each stage decodes its respective binary digit for one analog sample while the other stages are decoding their respective binary digits of other analog samples.
摘要翻译： 公开了一种使用多个具有相同参考电压输入的比较器的模拟 - 数字转换器电路。 在每个比较器级开发加和减二进制“位权重”。 选择一个阶段的正或负比特权重允许添加或减少二进制分数。 比较器级的数量仅需要等于输出中期望的数字位置的数量，而不是每个量化电平具有一个比较器。 比较器级在多个高速波形的控制下以“波”或“流水线”的方式工作，使得每个级对其一个模拟采样的相应二进制数进行解码，而其他级解码其相应二进制数位的其他 模拟样品。
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公开(公告)号：US4138666A
公开(公告)日：1979-02-06
申请号：US852233
申请日：1977-11-17
CPC分类号： H03M1/0604
摘要： A charge transfer circuit of the type including first and second capacitors and a charge transfer transistor for transferring discrete packets of charge from the first to the second capacitor is disclosed. The charge transfer circuit includes a feedback circuit which recharges the first capacitor to a value which varies as a function of the threshold voltage of the charge transfer transistor. As a result, the magnitude of the charge packets transferred by the charge transfer remain at a predetermined value irrespective of variations in the threshold voltage of the transistor.
摘要翻译： 公开了一种包括第一和第二电容器的电荷转移电路，以及用于从第一电容器转移到第二电容器的电荷转移晶体管。 电荷转移电路包括反馈电路，其将第一电容器充电到根据电荷转移晶体管的阈值电压变化的值。 结果，不管晶体管的阈值电压的变化如何，通过电荷转移传送的电荷包的大小保持在预定值。
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公开(公告)号：US4336525A
公开(公告)日：1982-06-22
申请号：US137651
申请日：1980-04-07
CPC分类号： H03M1/16
摘要： A four bit subtractor analog to digital converter provides direct conversion of analog voltage signals into binary or binary coded decimal output signals for digital display or digital signal processing. The analog to digital converter utilizes a plurality of signal processing sections, each section being designed to provide a binary output with the composite output bits being indicative of the analog input signal. In processing the analog signal an operational amplifier compares the input analog signal with a reference voltage in each section. Each section either passes or rejects the analog signal input in response to this comparison voltage. If the signal is rejected by a section it is passed to the next section where the same type of comparison takes place, if the signal is accepted by the operational amplifier and operated on, a comparator responsive to the amplifier output changes state providing a binary one output instead of a binary zero. A change in the comparator output signal to a binary one causes a field effect transistor switch to change states thereby supplying the operational amplifier output signal to subsequent signal processing sections instead of the originally supplied analog signal input. Subsequent sections operate in an identical manner with a systematic reduction in the comparison or reference voltage for providing digital signal processing. An amplifier at the end of each signal processing stage operates on the residual analog signal input to that amplifier to prepare the signal for processing in subsequent stages and thereby maintain signal integrity with no loss of signal level.
摘要翻译： 模数转换器的四位减法器将模拟电压信号直接转换为二进制或二进制编码十进制输出信号，用于数字显示或数字信号处理。 模数转换器利用多个信号处理部分，每个部分被设计成提供二进制输出，复合输出位指示模拟输入信号。 在处理模拟信号时，运算放大器将输入的模拟信号与每个部分的参考电压进行比较。 每个部分响应于该比较电压而通过或拒绝模拟信号输入。 如果该信号被一个部分拒绝，则它被传递到相同类型的比较发生的下一个部分，如果信号被运算放大器接受并被操作，则响应于放大器输出的比较器改变提供二进制的状态 输出而不是二进制零。 将比较器输出信号改变为二进制信号导致场效应晶体管开关改变状态，从而将运算放大器输出信号提供给后续的信号处理部分，而不是原始提供的模拟信号输入。 随后的部分以相同的方式工作，系统地减少用于提供数字信号处理的比较或参考电压。 每个信号处理阶段结束时的放大器对输入到该放大器的残留模拟信号进行操作，以准备用于后续级处理的信号，从而保持信号完整性而不会损失信号电平。
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公开(公告)号：US4325055A
公开(公告)日：1982-04-13
申请号：US088670
申请日：1979-10-26
摘要： An analog-to-digital converter using MOS-charge redistribution techniques performs an N-bit analog-to-digital conversion with only N steps, using two capacitors. These capacitors enable obtaining at each step a reference voltage VRi=VR/2.sup.i and either to compute a voltage Vi+1=Vi-VRi if the i.sup.th bit is equal to 1 or to retain the voltage Vi+1=Vi if the i.sup.th bit is equal to 0. At each step, the voltage Vi is compared to the reference voltage VRi in order to determine the value of the i.sup.th bit.
摘要翻译： 使用MOS电荷再分配技术的模数转换器使用两个电容器仅执行N个步进的N位模数转换。 这些电容器可以在每个步骤中获得参考电压VRi = VR / 2i，并且如果第i个位等于1则计算电压Vi + 1 = Vi-VRi，或者如果第i个位保持电压Vi + 1 = Vi 等于0.在每个步骤中，将电压Vi与参考电压VRi进行比较，以便确定第i位的值。
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5.发明授权
公开(公告)号：US4250494A
公开(公告)日：1981-02-10
申请号：US56070
申请日：1979-07-09
摘要： A charge transfer analog-to-digital converter is provided with means to establish the potential across a large storage well at a comparator threshold voltage at the initiation of a cycle. Charge transfer circuitry is also provided for transferring, into the large potential well, charge packets of size dependent only upon the value of a charge packet capacitance and a scaling voltage. Parasitic capacitance effects are essentially eliminated.
摘要翻译： 电荷转移模数转换器具有在周期开始时以比较器阈值电压建立跨越大存储阱的电位的装置。 还提供电荷转移电路用于将大小依赖于电荷分组电容和缩放电压的值传送到大电位阱中。 寄生电容效应基本消除。
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公开(公告)号：US4647904A
公开(公告)日：1987-03-03
申请号：US605100
申请日：1984-04-30
申请人： John C. Kuklewicz
发明人： John C. Kuklewicz
CPC分类号： H03M1/368
摘要： A folding-type A/D converter for converting an analog input signal to an n-bit digital code, the A/D converter having a transfer function dividing the analog input signal into at least n-1 segments, each such n-1 segment having an amplitude level corresponding to the significance of a given bit of the digital code and having linear parts which are mirror images of one another extending over 2.sup.n transition levels L. The A/D converter includes voltage-current converters for converting voltage input signals to current signals, a plurality of circuit stages for producing the linear parts in the current domain in response to the current signals, and a converter for converting the linear parts to a logic 1 or logic 0 of the bits of the digital code.
摘要翻译： 一种用于将模拟输入信号转换成n位数字码的折叠型A / D转换器，所述A / D转换器具有将所述模拟输入信号划分为至少n-1个段的传递函数，每个这样的n-1段 具有对应于数字码的给定位的重要性的幅度电平，并且具有彼此延伸超过2n个过渡电平L的镜像的线性部分.A / D转换器包括电压 - 电流转换器，用于将电压输入信号转换为 电流信号，用于响应于当前信号产生当前域中的线性部分的多个电路级，以及用于将线性部分转换为数字代码的位的逻辑1或逻辑0的转换器。
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公开(公告)号：US4535318A
公开(公告)日：1985-08-13
申请号：US552589
申请日：1983-11-16
CPC分类号： H03M1/1038 , H03M1/403
摘要： A calibration circuit for a recirculation of remainder analog-to-digital (A/D) converter heuristically solves a multiple variable conversion equation. Input analog calibration and analog reference signals are compared in a comparator, and when the two signals have a predetermined relationship, the comparator generates an indicator signal. A microprocessor determines a first pattern of digital reference signals that, together with digital calibration signals generated by the microprocessor, causes the comparator to generate the indicator signal and a second pattern of digital reference signals that, together with the input analog calibration signals, causes the comparator to generate the indicator signal. The difference between the first and second patterns of digital reference signals is stored as conversion coefficients.
摘要翻译： 余数模数转换器（A / D）转换器的循环校准电路启发式地解决了多变量转换方程。 在比较器中比较输入模拟校准和模拟参考信号，当两个信号具有预定的关系时，比较器产生指示信号。 微处理器确定第一模式的数字参考信号，其连同由微处理器产生的数字校准信号一起使得比较器产生指示符信号和第二模式的数字参考信号，其与输入的模拟校准信号一起导致 比较器产生指示信号。 数字参考信号的第一和第二模式之间的差被存储为转换系数。
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公开(公告)号：US4185275A
公开(公告)日：1980-01-22
申请号：US928163
申请日：1978-07-26
申请人： Robert L. Carbrey
发明人： Robert L. Carbrey
摘要： The disclosed analog to digital converter employs a single signal propagation path thereby necessitating only one holding capacitor (101) per stage (STAGE 1) of coding. The first terminal (B) of each holding capacitor (101) is connected to a reference voltage (L1) such as a resistive divider (106, 116, 126, 136, 146, 150, 151, V.sub.HI) which has binary weighted taps (L1-L5). The other terminal (A) of each holding capacitor (101) is connected to the analog signal input (INPUT). The reference voltage (L1) and the analog sample (V1) are compared and, for a zero decision, the stored analog sample (V1) is directly passed on to the subsequent stage (STAGE 2) by a buffer circuit (102). For a one decision, the aforementioned first terminal (B) of the holding capacitor (101) is switched from the tap of the resistive divider to circuit ground thereby subtracting that binary weight (L1) from the signal (V1) stored on the holding capacitor (101). When the subtraction operation is complete, the remaining signal (V1-L1) is passed through the buffer circuit (102) to the subsequent stage (STAGE 2).
摘要翻译： 所公开的模数转换器采用单个信号传播路径，从而每个阶段（STAGE 1）只需要一个保持电容（101）。 每个保持电容器（101）的第一端子（B）连接到诸如具有二进制加权抽头的电阻分压器（106,116,126,136,146,150,151，VHI）的参考电压（L1） L1-L5）。 每个保持电容器（101）的另一个端子（A）连接到模拟信号输入端（INPUT）。 比较参考电压（L1）和模拟采样（V1），对于零判定，存储的模拟采样（V1）由缓冲电路（102）直接传递到后级（STAGE 2）。 对于一个决定，保持电容器（101）的上述第一端子（B）从电阻分压器的抽头切换到电路接地，从而从存储在保持电容器上的信号（V1）减去该二进制权重（L1） （101）。 当减法运算完成时，剩余信号（V1-L1）通过缓冲电路（102）传递到后级（STAGE2）。
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9.发明授权Method and apparatus for sampling and holding an analog input voltage which eliminates offset voltage error 失效用于采样和保持模拟输入电压的方法和装置，消除偏移电压误差
公开(公告)号：US4119960A
公开(公告)日：1978-10-10
申请号：US767735
申请日：1977-02-11
申请人： Lorimer K. Hill
发明人： Lorimer K. Hill
CPC分类号： G11C27/026 , H03M1/1295
摘要： A sample and hold circuit uses two amplifiers the second being a Miller integrator and the first a comparator which compares the feed back stored capacitor voltage to the sampled voltage to bring the stored voltage of the capacitor to the sample voltage value. This stored voltage will have included in it the offset voltage of the first amplifier. However on readout this offset voltage is eliminated by disconnecting the sample input and also the connection between the output of the first amplifier and the input of the second and instead connecting the output of the first amplifier to the sample input and taking the output from this interconnection line. Since the noninverting or plus terminal of the first amplifier has impressed upon it the stored voltage of the capacitor the unwanted offset voltage is effectively subtracted. The foregoing sample and hold circuit also finds preferred use in a 12 bit recirculating A to D converter where cumulative offset errors would cause error. In such a configuration one of the sample and hold circuits can have the feedback interconnection of the first amplifier configured to perform suitable multiplication and subtraction, for example, for a Gray code. Here a second sample and hold circuit stores successive computational results.
摘要翻译： 采样和保持电路使用两个放大器，第二个是米勒积分器，第一个是比较器，将反馈存储的电容电压与采样电压进行比较，以将电容器的存储电压调到采样电压值。 该存储的电压将包括第一放大器的偏移电压。 然而，在读出时，通过断开采样输入以及第一放大器的输出与第二放大器的输入之间的连接以及将第一放大器的输出连接到采样输入并从该互连中输出，消除该偏移电压 线。 由于第一放大器的同相或正端子已经印在其上，电容器的存储电压有效地减去不需要的偏移电压。 上述采样和保持电路也可用于12位循环A到D转换器，其中累积偏移误差会导致误差。 在这种配置中，采样和保持电路之一可以具有被配置为执行适当的乘法和减法的第一放大器的反馈互连，例如对于格雷码。 这里第二采样和保持电路存储连续的计算结果。
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公开(公告)号：US4593268A
公开(公告)日：1986-06-03
申请号：US468720
申请日：1983-02-22
申请人： Robert A. Blauschild
发明人： Robert A. Blauschild
CPC分类号： H03M1/44
摘要： An absolute-value analog-to-digital converter containing a chain of matched main absolute-value differential amplifiers (A.sub.1 -A.sub.N) has a gain control for regulating the gain of each main amplifier utilizing an auxiliary absolute-value differential amplifier (A.sub.GC) matched to the main amplifiers. An offset control in the converter drives the offsets of the amplifiers toward zero by using a further absolute-value differential amplifier (A.sub.OC) matched to the other amplifiers. The gain and offset control are implemented with suitable feedback circuitry.
摘要翻译： 包含匹配主绝对值差分放大器（A1-AN）链的绝对值模数转换器具有增益控制，用于利用匹配的辅助绝对值差分放大器（AGC）来调节每个主放大器的增益 到主放大器。 转换器中的偏移控制通过使用与其他放大器匹配的另一绝对值差分放大器（AOC）将放大器的偏移驱动为零。 利用合适的反馈电路来实现增益和偏移控制。
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