公开(公告)号：US06700149B2

公开(公告)日：2004-03-02

申请号：US10113421

申请日：2002-04-01

申请人： Thomas Tille ,  Doris Schmitt-Landsiedel ,  Jens Sauerbrey

发明人： Thomas Tille ,  Doris Schmitt-Landsiedel ,  Jens Sauerbrey

IPC分类号： H01L27088

CPC分类号： H01L27/0805 ,  H01L29/94

摘要： A circuit configuration for providing a capacitance includes short-channel MOS transistors that are reverse-connected in series or in parallel, and that have the same channel type. When the short-channel MOS transistors are operated exclusively in the depletion mode in the required voltage range, the useful capacitance is increased, because of intrinsic capacitances, as compared with circuit configurations having conventional long-channel MOS transistors. These circuits greatly reduce the area taken up and reduce the costs.

摘要翻译： 用于提供电容的电路配置包括串联或并联反向并且具有相同通道类型的短沟道MOS晶体管。 当短沟道MOS晶体管仅在所需电压范围内的耗尽模式下工作时，与具有常规长沟道MOS晶体管的电路配置相比，由于固有电容，有用电容增加。 这些电路大大减少了占用的面积并降低了成本。

公开(公告)号：US06323561B1

公开(公告)日：2001-11-27

申请号：US08987455

申请日：1997-12-09

申请人： Mark I. Gardner ,  Fred N. Hause ,  Charles E. May

发明人： Mark I. Gardner ,  Fred N. Hause ,  Charles E. May

IPC分类号： H01L27088

CPC分类号： H01L29/66598 ,  H01L21/266 ,  H01L29/665 ,  H01L29/6659 ,  H01L29/7833

摘要： The formation of a spacer for precise salicide formation is disclosed. In one embodiment, a method includes four steps. In the first step, at least one first spacer is formed, where each spacer is adjacent to an edge of a gate on a substrate and has a triangular geometry. In the second step, an ion implantation is applied to form a graded lightly doped region within the substrate underneath each spacer, the region corresponding to the triangular geometry of the spacer. In the third step, at least one second spacer is formed, where each second spacer overlaps a corresponding first spacer. In the fourth step, a metal silicide within the substrate is formed immediately adjacent to each second spacer.

摘要翻译： 公开了形成用于精确的自对准硅化物形成的间隔物。 在一个实施例中，一种方法包括四个步骤。 在第一步骤中，形成至少一个第一间隔物，其中每个间隔物邻近衬底上的栅极的边缘并且具有三角形几何形状。 在第二步骤中，施加离子注入以在每个间隔物下面的衬底内形成渐变的轻掺杂区域，该区域对应于间隔物的三角形几何形状。 在第三步骤中，形成至少一个第二间隔物，其中每个第二间隔物与相应的第一间隔物重叠。 在第四步骤中，衬底内的金属硅化物紧邻每个第二间隔物形成。

公开(公告)号：US06661057B1

公开(公告)日：2003-12-09

申请号：US09056836

申请日：1998-04-07

申请人： Robert Dawson ,  Mark I. Gardner ,  Frederick N. Hause ,  H. Jim Fulford, Jr. ,  Mark W. Michael ,  Bradley T. Moore ,  Derick J. Wristers

发明人： Robert Dawson ,  Mark I. Gardner ,  Frederick N. Hause ,  H. Jim Fulford, Jr. ,  Mark W. Michael ,  Bradley T. Moore ,  Derick J. Wristers

IPC分类号： H01L27088

CPC分类号： H01L21/76843 ,  H01L21/28518 ,  H01L21/32053 ,  H01L21/76802 ,  H01L21/76855 ,  H01L29/66484 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7831 ,  H01L29/7833 ,  Y10S257/90

摘要： A transistor is formed in an active area having a segmented gate structure. The segmented gate structure advantageously provides for dynamic control of a channel region formed within the transistor. Lightly doped source and drain (LDD) regions are formed aligned to a gate electrode. After forming an insulating layer adjacent the exposed surfaces of the gate electrode, conductive spacers are formed disposed overlying the LDD regions. These spacers are electrically isolated from the gate electrode by the insulating layer. Heavily doped source and drain (S/D) regions are formed which are aligned to the spacers and make electrical contact, for example through a salicide process, supplied to the conductive spacer, the gate electrode, and the S/D regions. The described structure advantageously supplies dynamic control of the channel region through dynamic, independent control of the LDD portions of the S/D regions.

摘要翻译： 晶体管形成在具有分段栅极结构的有源区中。 分段栅结构有利地提供了在晶体管内形成的沟道区的动态控制。 轻掺杂的源极和漏极（LDD）区域形成为与栅电极对准。 在与栅电极的暴露表面相邻形成绝缘层之后，形成布置在LDD区域上方的导电间隔物。 这些间隔物通过绝缘层与栅电极电隔离。 形成重掺杂的源极和漏极（S / D）区域，其与间隔物对准，并且例如通过提供给导电间隔物，栅电极和S / D区域的自对准硅化物工艺进行电接触。 所描述的结构有利地通过对S / D区域的LDD部分的动态独立控制来提供通道区域的动态控制。

公开(公告)号：US06512275B1

公开(公告)日：2003-01-28

申请号：US09473908

申请日：1999-12-28

申请人： Louis Lu-chen Hsu ,  Jack Allan Mandelman

发明人： Louis Lu-chen Hsu ,  Jack Allan Mandelman

IPC分类号： H01L27088

CPC分类号： H01L29/785 ,  H01L27/088 ,  H01L27/092 ,  Y10S257/90

摘要： A semiconductor apparatus and method for making the same is disclosed herein in which the semiconductor apparatus includes a first active device formed in a mesa region of semiconductor material formed on one or more sidewalls of an isolation region, and a conductive path which extends from the active device in a linear direction of the mesa. An embodiment is disclosed in which a plurality of active devices are formed in the mesa region and electrically connected thereby.

摘要翻译： 本发明公开了半导体装置及其制造方法，其中半导体装置包括形成在隔离区的一个或多个侧壁上形成的半导体材料的台面区域中的第一有源器件，以及从该有源器件延伸的导电路径 装置在台面的线性方向。 公开了一种实施例，其中在台面区域中形成多个有源器件并由此电连接。

公开(公告)号：US06172411B2

公开(公告)日：2001-01-09

申请号：US09208921

申请日：1998-12-10

申请人： Li-chih Chao ,  Jhon-Jhy Liaw ,  Yuan-Chang Huang ,  Jin-Yuan Lee

发明人： Li-chih Chao ,  Jhon-Jhy Liaw ,  Yuan-Chang Huang ,  Jin-Yuan Lee

IPC分类号： H01L27088

CPC分类号： H01L21/76897 ,  H01L21/31116 ,  Y10S257/90

摘要： A self-aligned structure and method of etching contact holes in the self-aligned structure are described. The dielectric materials, etching methods, and etchants are chosen to provide high selectivity etching. The structure comprises an electrode with a silicon oxy-nitride cap and silicon oxy-nitride spacers on the sidewalls of the electrode and the cap. An etch stop layer of silicon nitride is deposited over the substrate covering the spacers and cap. A layer of silicon oxide is deposited over the etch stop layer. Etching methods and etchants are used which provide a ratio of the etching rate of silicon oxide to the etching rate of silicon nitride or silicon oxy-nitride of at least eight and a ratio of the etching rate of silicon nitride to the etching rate of silicon oxy-nitride of at least two.

摘要翻译： 描述了自对准结构和蚀刻自对准结构中的接触孔的方法。 选择介电材料，蚀刻方法和蚀刻剂以提供高选择性蚀刻。 该结构包括在电极和盖的侧壁上具有氮氧化硅帽和氮氧化硅间隔物的电极。 氮化硅的蚀刻停止层沉积在覆盖间隔物和盖的衬底上。 氧化硅层沉积在蚀刻停止层上。 使用蚀刻方法和蚀刻剂，其提供氧化硅的蚀刻速率与氮化硅或氮氧化硅的蚀刻速率的比率至少为8，氮化硅的蚀刻速率与硅氧化物的蚀刻速率的比率 至少两个。

公开(公告)号：US06806584B2

公开(公告)日：2004-10-19

申请号：US10277907

申请日：2002-10-21

申请人： Ka Hing Fung ,  Percy V. Gilbert

发明人： Ka Hing Fung ,  Percy V. Gilbert

IPC分类号： H01L27088

CPC分类号： H01L21/823864 ,  Y10S257/90

摘要： A semiconductor device structure includes at least two field effect transistors formed on same substrate, the first field effect transistor includes a spacer having a first width, the second field effect transistor includes a spacer having a second width, the first width being different than said second width. Preferably, the first width is narrower than the second width.

摘要翻译： 半导体器件结构包括形成在同一衬底上的至少两个场效应晶体管，所述第一场效应晶体管包括具有第一宽度的间隔物，所述第二场效应晶体管包括具有第二宽度的间隔物，所述第一宽度不同于所述第二宽度 宽度。 优选地，第一宽度比第二宽度窄。

公开(公告)号：US06794764B1

公开(公告)日：2004-09-21

申请号：US10382726

申请日：2003-03-05

申请人： Tazrien Kamal ,  Mark T. Ramsbey ,  Hidehiko Shiraiwa ,  Fred T K Cheung

发明人： Tazrien Kamal ,  Mark T. Ramsbey ,  Hidehiko Shiraiwa ,  Fred T K Cheung

IPC分类号： H01L27088

CPC分类号： H01L27/11568 ,  H01L27/115 ,  H01L2224/48247 ,  H01L2224/85464 ,  H01L2924/01012 ,  H01L2924/01019 ,  H01L2924/01021 ,  H01L2924/01057 ,  H01L2924/01087 ,  H01L2924/10253 ,  H01L2924/13091 ,  H01L2924/14 ,  Y10S257/90 ,  H01L2924/00

摘要： The present invention relates to a memory array comprising a substrate and a plurality of bitlines having contacts and a plurality of wordlines intersecting the bitlines. A protective spacer is used to separate the bitline contacts from the wordlines adjacent to the bitline contacts to prevent damage caused during the formation of the bitline contacts. The present invention also relates to a method of forming the memory array.

摘要翻译： 本发明涉及包括基板和多个位线的存储器阵列，该位线具有触点和与位线相交的多个字线。 保护间隔器用于将位线触点与位线触点相邻的字线分开，以防止在形成位线触点期间造成的损坏。 本发明还涉及形成存储器阵列的方法。

公开(公告)号：US06545370B1

公开(公告)日：2003-04-08

申请号：US09679375

申请日：2000-10-05

申请人： Minh Van Ngo ,  Christy Mei-Chu Woo ,  Paul R. Besser

发明人： Minh Van Ngo ,  Christy Mei-Chu Woo ,  Paul R. Besser

IPC分类号： H01L27088

CPC分类号： H01L29/665 ,  H01L29/4983 ,  H01L29/6656

摘要： Bridging between nickel silicide layers on a gate electrode and source/drain regions along silicon nitride sidewall spacers is prevented by employing composite silicon nitride sidewall spacers comprising an outer layer having reduced free silicon. Embodiments include forming composite silicon nitride sidewall spacers comprising an inner silicon nitride layer, having a refractive index of about 1.95 to about 2.05 and a thickness of about 450 Å to about 550 Å, on the side surfaces of the gate electrode and an outer silicon nitride layer, having a refractive index to less than about 1.95 and a thickness of about 350 Å to about 450 Å.

摘要翻译： 通过使用复合氮化硅侧壁间隔物来防止在栅电极上的硅化镍层和沿着氮化硅侧壁间隔物的源极/漏极区之间的桥接，所述复合氮化硅侧壁间隔物包括具有减少的自由硅的外层。 实施例包括形成复合氮化硅侧壁间隔物，其包括内部氮化硅层，折射率为约1.95至约2.05，厚度约为450至大约的厚度在栅电极和外部氮化硅 层，具有小于约1.95的折射率和约350至约的厚度。

公开(公告)号：US06225661B1

公开(公告)日：2001-05-01

申请号：US09145786

申请日：1998-09-02

申请人： Judy Xilin An ,  Bin Yu ,  Ming-Ren Lin

发明人： Judy Xilin An ,  Bin Yu ,  Ming-Ren Lin

IPC分类号： H01L27088

CPC分类号： H01L21/28194 ,  H01L29/42368 ,  H01L29/513 ,  H01L29/518 ,  H01L29/66545 ,  H01L2924/0002 ,  Y10S257/90 ,  Y10S438/981 ,  H01L2924/00

摘要： A field effect transistor (FET) is formed on a silicon substrate, with a nitride gate insulator layer being deposited on the substrate and an oxide gate insulator layer being deposited on the nitride layer to insulate a gate electrode from source and drain regions in the substrate. The gate material is then removed to establish a gate void, and spacers are deposited on the sides of the void such that only a portion of the oxide layer is covered by the spacers. Then, the unshielded portion of the oxide layer is removed, thus establishing a step between the oxide and nitride layers that overlays the source and drain extensions under the gate void to reduce subsequent capacitive coupling and charge carrier tunneling between the gate and the extensions. The spacers are removed and the gate void is refilled with gate electrode material.

摘要翻译： 在硅衬底上形成场效应晶体管（FET），其中氮化物栅极绝缘体层沉积在衬底上，并且氧化物栅极绝缘体层沉积在氮化物层上以使栅电极与衬底中的源极和漏极区域绝缘 。 然后去除栅极材料以建立栅极空隙，并且间隔物沉积在空隙的侧面上，使得只有一部分氧化物层被间隔物覆盖。 然后，去除氧化物层的非屏蔽部分，从而在栅极空隙下的源极和漏极延伸层之间建立氧化物层和氮化物层之间的步骤，以减少栅极和延伸部之间的后续电容耦合和电荷载流子隧道。 去除间隔物，并用栅电极材料重新填充栅极空隙。

公开(公告)号：US06809425B1

公开(公告)日：2004-10-26

申请号：US10641610

申请日：2003-08-15

申请人： Bomy Chen ,  Isao Nojima ,  Hung Q. Nguyen

发明人： Bomy Chen ,  Isao Nojima ,  Hung Q. Nguyen

IPC分类号： H01L27088

CPC分类号： H03K19/17748 ,  H01L27/101 ,  H03K19/1778 ,  Y10S257/901

摘要： A nonvolatile reprogrammable switch for use in a PLD or FPGA has a nonvolatile memory cell connected to the gate of an MOS transistor, which is in a well, with the terminals of the MOS transistor connected to the source of the signal and to the circuit. The nonvolatile memory cell is of a split gate type having a first region and a second region, with a channel therebetween. The cell has a floating gate positioned over a first portion of the channel, which is adjacent to the first region and a control gate positioned over a second portion of the channel, which is adjacent to the second region. The second region is connected to the gate of the MOS transistor. The cell is programmed by injecting electrons from the channel onto the floating gate by hot electron injection mechanism. The cell is erased by Fowler-Nordheim tunneling of the electrons from the floating gate to the control gate. As a result, no high voltage is ever applied to the second region during program or erase. In addition, a MOS FET transistor has a terminal connected to the well, and another end to a voltage source, with the gate connected to the non-volatile memory cell. The switch also has a circuit element connecting the gate of the MOS transistor to a voltage source. The threshold voltage of the well can be dynamically changed by turning on/off the MOS FET transistor.

摘要翻译： 用于PLD或FPGA的非易失性可重新编程开关具有连接到MOS晶体管的栅极的非易失性存储单元，MOS晶体管位于阱中，MOS晶体管的端子连接到信号源和电路。 非易失性存储单元是具有第一区域和第二区域的分离栅极类型，其间具有沟道。 电池具有位于通道第一部分上方的浮动栅极，该第一部分与第一区域相邻，并且控制栅极位于与第二区域相邻的通道的第二部分上方。 第二区域连接到MOS晶体管的栅极。 通过热电子注入机制将电子从通道注入到浮动栅上来编程电池。 Fowler-Nordheim将电池从浮动栅极隧穿到控制栅极，从而消除电池。 因此，在编程或擦除期间，不会对第二区域施加高电压。 此外，MOS FET晶体管具有连接到阱的端子，另一端连接到电压源，栅极连接到非易失性存储单元。 该开关还具有将MOS晶体管的栅极连接到电压源的电路元件。 通过接通/关断MOS FET晶体管可以动态地改变阱的阈值电压。