公开(公告)号：US11864376B2

公开(公告)日：2024-01-02

申请号：US17370673

申请日：2021-07-08

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Chin-Shan Wang ,  Shun-Yi Lee

IPC: H01L27/108 ,  H01L21/00 ,  H10B12/00 ,  H01L21/8238

CPC classification number: H10B12/373 ,  H10B12/03 ,  H10B12/0387 ,  H10B12/056 ,  H10B12/36 ,  H10B12/488 ,  H01L21/823878

Abstract: A method of making a semiconductor device includes forming a first transistor on a substrate, wherein forming the first transistor comprises forming a first source/drain electrode in the substrate. The method further includes forming a second transistor on the substrate, wherein forming the second transistor comprises forming a second source/drain electrode. The method further includes forming an insulating layer extending into the substrate, wherein the insulating layer directly contacts the first source/drain electrode and the second source/drain electrode, a top surface of the insulating layer is above a top surface of the substrate.

公开(公告)号：US12127396B2

公开(公告)日：2024-10-22

申请号：US17874512

申请日：2022-07-27

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyunji Song ,  Jaehoon Kim ,  Kwangho Park ,  Yonghoon Son ,  Gyeonghee Lee ,  Seungjae Jung

IPC: H10B12/00

CPC classification number: H10B12/373 ,  H10B12/0387

Abstract: An integrated circuit device includes a plurality of semiconductor layers stacked on a substrate to overlap each other in a vertical direction and longitudinally extending along a first horizontal direction. The plurality of semiconductor layers may have different thicknesses in the vertical direction.

公开(公告)号：US11903185B2

公开(公告)日：2024-02-13

申请号：US17560050

申请日：2021-12-22

Applicant: SK hynix Inc.

Inventor： Kun-Young Lee ,  Sun-Young Kim

IPC: H10B12/00

CPC classification number: H10B12/373 ,  H10B12/0383 ,  H10B12/09 ,  H10B12/50

Abstract: Disclosed is a vertically stacked 3D memory device, and the memory device may include a bit line extended vertically from a substrate, and including a first vertical portion and a second vertical portion, a vertical active layer configured to surround the first and second vertical portions of the bit line, a word line configured to surround the vertical active layer and the first vertical portion of the bit line, and a capacitor spaced apart vertically from the word line, and configured to surround the vertical active layer and the second vertical portion of the bit line.

公开(公告)号：US20240032281A1

公开(公告)日：2024-01-25

申请号：US18223560

申请日：2023-07-19

Applicant: Invention And Collaboration Laboratory Pte. Ltd.

Inventor： Chao-Chun Lu ,  Ming-Hong Kuo ,  Chun-Nan Lu

IPC: H10B12/00

CPC classification number: H10B12/373 ,  H10B12/482

Abstract: A memory cell structure includes a silicon substrate, a transistor, and a capacitor. The silicon substrate has a silicon surface. The transistor is coupled to the silicon surface, the transistor includes a gate structure, a first conductive region, and a second conductive region. The capacitor has a signal electrode and a counter electrode, the capacitor is over the transistor, and the signal electrode is electrically coupled to the second conductive region of the transistor and isolated from the first conductive region of the transistor. The counter electrode includes a plurality of sub-electrodes electrically connected with each other.

公开(公告)号：US12082400B2

公开(公告)日：2024-09-03

申请号：US17308071

申请日：2021-05-05

Applicant: Etron Technology, Inc.

Inventor： Chao-Chun Lu

IPC: H10B12/00

CPC classification number: H10B12/373

Abstract: A memory cell structure includes a silicon substrate, a transistor, a bit line, and a capacitor. The silicon substrate has a silicon surface. The transistor is coupled to the silicon surface, wherein the transistor includes a gate structure, a first conductive region, and a second conductive region. The bit line is electrically coupled to the first conductive region of the transistor and positioned under the silicon surface. The capacitor is over the transistor and electrically coupled to the second conductive region of the transistor.

公开(公告)号：US20230232607A1

公开(公告)日：2023-07-20

申请号：US17420124

申请日：2020-12-03

Applicant: ChangXin Memory Technologies, Inc.

Inventor： Jinil LEE

IPC: H10B12/00

CPC classification number: H10B12/0387 ,  H10B12/373 ,  H01L28/91

Abstract: The present disclosure is in the field of semiconductor devices, in particular, to a semiconductor structure and a method of forming the same. The semiconductor structure includes: a substrate with a trench extending in a direction of the substrate; a capacitor fabricated in the trench, the capacitor includes a lower electrode disposed on an inner wall of the trench, a dielectric combination layer disposed on the lower electrode, and an upper electrode disposed on the dielectric combination layer; the dielectric combination layer includes a stacked structure composed of a nitride layer and an oxide layer. The device can increase the capacitance of the capacitor significantly and reduce the occurrence of charge leakage, thereby improving the electrical performance of the semiconductor memory device.

公开(公告)号：US20230180460A1

公开(公告)日：2023-06-08

申请号：US18165381

申请日：2023-02-07

Applicant: CHANGXIN MEMORY TECHNOLOGIES, INC.

Inventor： Zhongming LIU ,  Yexiao Yu ,  Longyang Chen

IPC: H10B12/00

CPC classification number: H10B12/315 ,  H10B12/482 ,  H10B12/488 ,  H10B12/0385 ,  H10B12/0387 ,  H10B12/373

Abstract: A memory device and a method for manufacturing a memory device are provided. The memory device includes: a substrate, and a plurality of first capacitors embedded in the substrate; a plurality of first vertical transistors and a plurality of second vertical transistors, in which the plurality of first vertical transistors and the plurality of second vertical transistors are arranged on the substrate, and in which each of the plurality of first vertical transistors is electrically connected to a respective one of the plurality of first capacitors; and a plurality of second capacitors arranged on the plurality of first vertical transistors and the plurality of second vertical transistors, in which each of the plurality of second capacitors is electrically connected to a respective one of the plurality of second vertical transistors.

公开(公告)号：US20240215218A1

公开(公告)日：2024-06-27

申请号：US18088944

申请日：2022-12-27

Applicant: HeFeChip Corporation Limited

Inventor： Liang LI ,  Chunyu WONG ,  John H. ZHANG ,  Yanzun LI ,  Huang LIU ,  Yuan Lung LIN ,  Haijiang YUAN ,  Chung-Chiang LIN

IPC: H10B12/00

CPC classification number: H10B12/0387 ,  H10B12/056 ,  H10B12/36 ,  H10B12/373

Abstract: A semiconductor structure and a method of forming it are disclosed by the present application. Deep trench capacitors are formed in a substrate, and fin contacts formed by upper portions of inner electrodes in the deep trench capacitors are connected to fins on a surface of the substrate. At least one of word lines formed on the substrate pass over and are separated by a word line isolation layer from the inner electrodes. The word line isolation layer covers portions of the inner electrodes between a buried oxide layer and the fin contacts, while the fins are exposed therefrom.

公开(公告)号：US20240107750A1

公开(公告)日：2024-03-28

申请号：US18522537

申请日：2023-11-29

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Chin-Shan WANG ,  Shun-Yi LEE

IPC: H10B12/00

CPC classification number: H10B12/373 ,  H10B12/03 ,  H10B12/0387 ,  H10B12/056 ,  H10B12/36 ,  H10B12/488 ,  H01L21/823878

Abstract: A method of making a semiconductor device includes forming a first transistor on a substrate, wherein forming the first transistor comprises forming a first source/drain electrode in the substrate. The method further includes forming a second transistor on the substrate, wherein forming the second transistor comprises forming a second source/drain electrode. The method further includes forming an insulating layer extending into the substrate, wherein the insulating layer directly contacts the first source/drain electrode, and the insulating layer extends above a top-most surface of the substrate.

公开(公告)号：US20240023316A1

公开(公告)日：2024-01-18

申请号：US18218209

申请日：2023-07-05

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： SZU-YAO CHANG

IPC: H10B12/00

CPC classification number: H10B12/373 ,  H10B12/05

Abstract: A semiconductor structure and a method of manufacturing a semiconductor structure are provided. The semiconductor structure includes a substrate, an upper structure, a vertical transistor an electrical pad. The upper structure is disposed on the substrate and defines a hole. The vertical transistor is disposed in the hole. The electrical pad is disposed in the hole and on the vertical transistor. A top surface of the electrical pad is substantially aligned with a topmost surface of the upper structure.