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公开(公告)号：US20150022388A1
公开(公告)日：2015-01-22
申请号：US14380134
申请日：2013-02-26
CPC分类号： H03M1/345 , H03M1/002 , H03M1/12 , H03M1/123 , H03M1/124 , H03M1/145 , H03M1/44 , H03M1/46 , H03M1/56
摘要： Method and device for converting analogue signals, of a plurality of pathways, into digital signals. A common circuit (2, 3) generates first analogue signals corresponding to high-order bits of digital signals For each pathway, a first means compares the first analogue signals with the signal to be converted. A first means (18) stores high-order bits corresponding to the value of a first analogue signal close to the signal to be converted. A means (9) stores the deviation between the analogue signal to be converted and said first detected value. A generator means (11, 12) generates a predetermined number of second analogue signals. A second means compares by successive approximations said second analogue signals with said deviation. A means (20) stores said low-order bits corresponding to the results arising from said second means of comparison. A means (22) assembles said high-order bits and said low-order bits.
摘要翻译： 用于将多个路径中的模拟信号转换为数字信号的方法和装置。 公共电路（2,3）产生与数字信号的高位相对应的第一模拟信号。对于每个路径，第一装置将第一模拟信号与要转换的信号进行比较。 第一装置（18）存储对应于接近待转换信号的第一模拟信号的值的高位。 A装置（9）存储要转换的模拟信号与所述第一检测值之间的偏差。 发生器装置（11,12）产生预定数量的第二模拟信号。 第二装置通过逐次逼近所述第二模拟信号与所述偏差进行比较。 A装置（20）存储对应于由所述第二比较装置产生的结果的所述低位。 一种装置（22）组装所述高阶位和所述低位位。
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公开(公告)号：US20150180500A1
公开(公告)日：2015-06-25
申请号：US14138261
申请日：2013-12-23
摘要： In one embodiment the quantizer includes a signal-to-phase converter configured to generate a phase signal according to an input signal and a phase difference digitization block configured to generate a quantization output according to differentiated samples of the phase signal, where the phase signal generated by the signal-to-phase converter has a sinusoidal shape.
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公开(公告)号：US3267461A
公开(公告)日：1966-08-16
申请号：US30470263
申请日：1963-08-26
申请人： HARMON WILLIAM R
发明人： HARMON WILLIAM R
CPC分类号： H03M1/345
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公开(公告)号：US09237002B2
公开(公告)日：2016-01-12
申请号：US14168604
申请日：2014-01-30
申请人： HBC SOLUTIONS, INC.
发明人： William Ty Chizevsky
CPC分类号： H04L7/0037 , H03M1/345 , H04B1/10 , H04H40/18 , H04H2201/20 , H04L7/033 , H04L25/061
摘要： One embodiment includes a circuit system. The system includes a power detector configured to convert an AC signal to a DC signal corresponding to a power amplitude associated with the AC signal. The AC signal can include a periodic signal power null. The system also includes a null-gating circuit comprising a logic switch that is activated to enable sampling of an amplitude of the DC signal and that is deactivated during the periodic signal power null. The system also includes an analog-to-digital converter (ADC) configured to convert the sampled DC signal to a digital signal. The system further includes a processor configured to process the digital signal.
摘要翻译： 一个实施例包括电路系统。 该系统包括功率检测器，其被配置为将AC信号转换成对应于与AC信号相关联的功率幅度的DC信号。 AC信号可以包括周期性信号功率为零。 该系统还包括一个零门电路，其包括一个逻辑开关，该逻辑开关被激活以能够采样DC信号的幅度，并且在周期性信号功率无效期间被去激活。 该系统还包括被配置为将采样的DC信号转换为数字信号的模拟 - 数字转换器（ADC）。 该系统还包括配置成处理数字信号的处理器。
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公开(公告)号：US3000006A
公开(公告)日：1961-09-12
申请号：US64742457
申请日：1957-03-20
申请人： MELPAR INC
发明人： WILLIAMS RICHARD E
IPC分类号： H03M1/00
CPC分类号： H03M1/345
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公开(公告)号：US09077370B2
公开(公告)日：2015-07-07
申请号：US14380134
申请日：2013-02-26
CPC分类号： H03M1/345 , H03M1/002 , H03M1/12 , H03M1/123 , H03M1/124 , H03M1/145 , H03M1/44 , H03M1/46 , H03M1/56
摘要： Method and device for converting analog signals, of a plurality of pathways, into digital signals. A common circuit (2, 3) generates first analog signals corresponding to high-order bits of digital signals. For each pathway, a first means compares the first analog signals with the signal to be converted. A first means (18) stores high-order bits corresponding to the value of a first analog signal close to the signal to be converted. A means (9) stores the deviation between the analog signal to be converted and said first detected value. A generator means (11, 12) generates a predetermined number of second analog signals. A second means compares by successive approximations said second analog signals with said deviation. A means (20) stores said low-order bits corresponding to the results arising from said second means of comparison. A means (22) assembles said high-order bits and said low-order bits.
摘要翻译： 用于将多个路径中的模拟信号转换为数字信号的方法和装置。 公共电路（2,3）产生对应于数字信号的高位的第一模拟信号。 对于每个路径，第一装置将第一模拟信号与要转换的信号进行比较。 第一装置（18）存储对应于接近待转换信号的第一模拟信号的值的高位。 A装置（9）存储要转换的模拟信号与所述第一检测值之间的偏差。 发生器装置（11,12）产生预定数量的第二模拟信号。 第二装置通过逐次逼近所述第二模拟信号与所述偏差进行比较。 A装置（20）存储对应于由所述第二比较装置产生的结果的所述低位。 一种装置（22）组装所述高阶位和所述低位位。
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7.发明申请SYSTEM FOR RNS BASED ANALOG-TO-DIGITAL CONVERSION AND INNER PRODUCT COMPUTATION 审中-公开基于RNS的模拟数字转换和内部产品计算系统公开(公告)号：US20140139365A1
公开(公告)日：2014-05-22
申请号：US14130051
申请日：2012-05-07
申请人： Chan Hua Vun , Benjamin Premkumar
发明人： Chan Hua Vun , Benjamin Premkumar
IPC分类号： H03M1/34
摘要： A system is proposed for forming the inner product of an input signal having a number of signal entries, with a pre-known vector. Each signal entry is represented in an RNS format. The residue for each modulus is represented as a string in which the number of components taking a first value is equal to the residue. Corresponding components of the strings for different input entries are used to obtain a summation value, and the summation values are accumulated. Since the components of the string are not associated with weight values, the accumulation of the summation values can be performed without using a scaling accumulator. Furthermore, an ADC is proposed which uses the input signal to generate an RNS representation of the signal based on a plurality of moduli. For each modulus, there is a corresponding Residue Number System (RNS) converter which includes a number of zero-crossing-based folding circuits equal to the modulus, and a comparator for each zero-crossing based folding circuit. The output of the comparators is used to form the RNS representation. This ADC is efficient in terms of the number of comparators it uses. Optionally, the RNS representation may be converted into a different digital representation.
摘要翻译： 提出了一种用于形成具有多个信号条目的输入信号的内积的系统，其具有预先知道的向量。 每个信号条目都以RNS格式表示。 每个模数的残差表示为采用第一个值的分量数等于残差的串。 用于不同输入条目的字符串的相应组件用于获得求和值，并累加求和值。 由于字符串的分量与权重值不相关，所以可以不使用缩放累加器来执行求和值的累积。 此外，提出了一种ADC，其使用输入信号以基于多个模量生成信号的RNS表示。 对于每个模数，存在相应的残余数系统（RNS）转换器，其包括等于模数的多个基于过零的折叠电路，以及用于每个过零的折叠电路的比较器。 比较器的输出用于形成RNS表示。 该ADC在其使用的比较器数量方面是有效的。 可选地，RNS表示可以被转换成不同的数字表示。
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8.发明授权Apparatus and method for processing analog signals using residue-based digital operations 失效使用基于残留的数字操作来处理模拟信号的装置和方法
公开(公告)号：US6144329A
公开(公告)日：2000-11-07
申请号：US92691
申请日：1998-06-05
摘要： In apparatus for digital processing to a sequence of numbers in binary format, each number is first converted to a base number and a residue number, the residue number being in a binary bit format. The processing is then performed using only the residue numbers. The digital processing is perfumed using binary addition, binary subtraction, and binary multiplication operations. After completion of the processing operation, the residue numbers are then converted into the original format. The folding analog-to-digital converter can be used to generate the residue binary bit numbers from an analog signal. This technique can reduce the apparatus required to perform such processing operations as FIR filtering and equalization.
摘要翻译： 在用于数字处理的装置中，以二进制格式的数字序列，首先将每个数字转换成一个基数和一个残差号，残差号是二进制位格式。 然后仅使用残基号进行处理。 数字处理使用二进制加法，二进制减法和二进制乘法运算进行加密。 在完成处理操作之后，剩余数字被转换成原始格式。 折叠模数转换器可用于从模拟信号产生残留二进制位数。 该技术可以减少执行FIR滤波和均衡等处理操作所需的设备。
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9.发明授权Analog-to-digital converter employing constant-current circuit incorporating MISFET 失效采用集成MISFET的恒流电路的模数转换器
公开(公告)号：US4250493A
公开(公告)日：1981-02-10
申请号：US925790
申请日：1978-07-18
申请人： Toshimasa Kihara , Toshiro Tsukada
发明人： Toshimasa Kihara , Toshiro Tsukada
摘要： The constant-current circuit consists of two MISFETs connected in series and a gate bias circuit for these MISFETs. The drain voltage of the first MISFET is maintained substantially constant by the source voltage of the second MISFET. The first MISFET does not sustain the channel length modulation, because its drain voltage is substantially constant. Consequently, a constant output current is obtained through the drain of the second MISFET.
摘要翻译： 恒流电路由串联连接的两个MISFET和这些MISFET的栅极偏置电路组成。 第一MISFET的漏极电压由第二MISFET的源极电压基本上保持恒定。 因为漏极电压基本上是恒定的，所以第一MISFET不支持沟道长度调制。 因此，通过第二MISFET的漏极获得恒定的输出电流。
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公开(公告)号：US4115766A
公开(公告)日：1978-09-19
申请号：US783342
申请日：1977-03-31
申请人： George Elwood Smith
发明人： George Elwood Smith
摘要： An analog electrical signal is converted into a binary digital signal by means of an arrangement of semiconductor surface potential wells. During operation, this arrangement converts the analog electrical signal into an analog signal charge packet in one of these potential wells and sequentially subtracts from this analog packet a sequence of reference charge packets representing the binary digital bits of the analog signal, provided that the then remaining signal charge packet is greater than the reference charge packet.
摘要翻译： 模拟电信号通过半导体表面势阱的布置被转换为二进制数字信号。 在操作期间，这种布置将模拟电信号转换为这些势阱中的一个中的模拟信号电荷分组，并且从该模拟分组中顺序地减去表示模拟信号的二进制数字位的参考电荷分组序列，只要当前剩余的 信号电荷包大于参考电荷包。
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