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    Lifetime mixed level non-volatile memory system
    1.
    发明授权
    Lifetime mixed level non-volatile memory system 有权

    公开(公告)号：US12136455B2

    公开(公告)日：2024-11-05

    申请号：US18613301

    申请日：2024-03-22

    Applicant: Vervain, LLC

    Inventor： G. R. Mohan Rao

    IPC: G11C11/56 ,  G06F11/10 ,  G06F12/02 ,  G11C16/16 ,  G11C16/34 ,  G11C29/00 ,  G11C29/52

    Abstract: A flash controller for managing at least one MLC non-volatile memory module and at least one SLC non-volatile memory module. The flash controller is adapted to determine if a range of addresses listed by an entry and mapped to said at least one MLC non-volatile memory module fails a data integrity test. In the event of such a failure, the controller remaps said entry to an equivalent range of addresses of said at least one SLC non-volatile memory module. The flash controller is further adapted to determine which of the blocks in the MLC and SLC non-volatile memory modules are accessed most frequently and allocating those blocks that receive frequent writes to the SLC non-volatile memory module and those blocks that receive infrequent writes to the MLC non-volatile memory module.

    LIFETIME MIXED LEVEL NON-VOLATILE MEMORY SYSTEM
    7.
    发明申请
    LIFETIME MIXED LEVEL NON-VOLATILE MEMORY SYSTEM 有权

    公开(公告)号：US20250054540A1

    公开(公告)日：2025-02-13

    申请号：US18926560

    申请日：2024-10-25

    Applicant: Vervain, LLC

    Inventor： G. R. Mohan Rao

    IPC: G11C11/56 ,  G06F11/10 ,  G06F12/02 ,  G11C16/16 ,  G11C16/34 ,  G11C29/00 ,  G11C29/52

    Abstract: An apparatus for storing data in a nonvolatile memory includes a controller configured to erase a group of physical memory cells in the nonvolatile memory. The controller is configured to write multiple bits of information to each of a first group of physical memory cells in the nonvolatile memory. The controller is configured to map a logical address range to a physical address range for the first group of physical memory cells in the nonvolatile memory. The controller is configured to determine if the first group of physical memory cells fails a data integrity test. If the first group of physical memory cells fails the data integrity test, the controller writes at least some of the information stored in the first group of physical memory cells to a second group of physical memory cells in the nonvolatile memory. The controller writes a single bit of information per cell in the second group of physical memory cells. The controller is configured to map the logical address range to a second physical address range for the second group of physical memory cells.

    LIFETIME MIXED LEVEL NON-VOLATILE MEMORY SYSTEM
    8.
    发明申请
    LIFETIME MIXED LEVEL NON-VOLATILE MEMORY SYSTEM 有权

    公开(公告)号：US20250014639A1

    公开(公告)日：2025-01-09

    申请号：US18893328

    申请日：2024-09-23

    Applicant: Vervain, LLC

    Inventor： G.R. Mohan Rao

    IPC: G11C11/56 ,  G06F11/10 ,  G06F12/02 ,  G11C16/16 ,  G11C16/34 ,  G11C29/00 ,  G11C29/52

    Abstract: A controller for managing at least one MLC non-volatile memory space including at least one MLC non-volatile memory element and at least one SLC non-volatile memory space including at least one SLC non-volatile memory element. The controller is adapted to determine if a range of addresses listed by an entry and mapped to the at least one MLC non-volatile memory element fails a data integrity test performed at the controller based upon received data retained at the controller and which received data is stored in the at least one MLC memory element as stored data. In the event of such a failure, the controller remaps said entry to an the at least one SLC non-volatile memory element.

    Lifetime mixed level non-volatile memory system
    10.
    发明授权
    Lifetime mixed level non-volatile memory system 有权

    公开(公告)号：US11854612B1

    公开(公告)日：2023-12-26

    申请号：US18373071

    申请日：2023-09-26

    Applicant: Vervain, LLC

    Inventor： G. R. Mohan Rao

    IPC: G11C11/56 ,  G06F12/02 ,  G11C16/34 ,  G06F11/10 ,  G11C29/52 ,  G11C29/00 ,  G11C16/16

    CPC classification number: G11C11/5635 ,  G06F11/1068 ,  G06F11/1072 ,  G06F12/0246 ,  G11C11/5621 ,  G11C11/5678 ,  G11C16/16 ,  G11C16/3495 ,  G11C29/52 ,  G11C29/76 ,  G06F2212/7202 ,  G11C2211/5641

    Abstract: A method for storing data comprises maintaining an address table for a memory space containing volatile memory and nonvolatile memory space. The nonvolatile memory space includes both multi-level cell (MLC) space and single level cell (SLC) space and the volatile memory includes a random access volatile memory element. An address table maps logical and physical addresses adaptable to the system by the address table. The mapping is performed as necessitated by the system to maximize lifetime maps data in at least one of volatile or nonvolatile memories. Storing received data within a controller memory associated with the at least one controller. Controlling access of the MLC and SLC nonvolatile memory elements and the random access volatile memory element for storage of the received data. Transferring the stored received data from the controller memory to a given one of the MLC nonvolatile memory elements in an associated MLC memory module, operable to store the received data in the given one given one of the MLC nonvolatile memory element as stored data. Retaining the received data in the random access volatile memory as retained data associated with the stored data. Performing a data integrity test on the stored data in the given one of the MLC nonvolatile memory elements in the associated one of the MLC memory modules after at least a Write access operation performed thereon. The performing of the data integrity test further comprising reading the stored data to the controller memory and comparing the stored data in the controller memory in the given one of the MLC nonvolatile memory elements to the retained data that was associated with the stored data in the random access volatile memory by the controller during the Write access operation. Remapping, responsive to a failure of the data integrity test performed on the stored data by the controller, the address space to a different physical range of addresses. Transferring data corresponding to the retained data to those remapped physical address from those physical addresses determined to have failed the data integrity test.

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