公开(公告)号：US06852990B1

公开(公告)日：2005-02-08

申请号：US09896381

申请日：2001-06-29

Applicant: Zhiyong Zhao ,  David Hendrix

Inventor： Zhiyong Zhao ,  David Hendrix

IPC: H01J37/02 ,  H01J61/00

CPC classification number: H01J37/026 ,  H01J2237/0041

Abstract: A method for electrostatic discharge depolarization is implemented. The buildup of charge on tool structures in fabrication tools for semiconductor processing may be expected to be of concern whenever high voltage is employed near the structure in a tool. The process herein includes selectively exposing the structure to a plasma for a selected time interval. The duration of the exposure time interval is sufficient to reduce the polarization of the structure whereby the forces due to the polarization do not interfere with the transport or movement of a wafer being processed.

Abstract translation: 实现了静电放电去极化的方法。 只要在工具中的结构附近采用高电压，可以预期在半导体处理用制造工具中的工具结构上的电荷的积累。 本文的方法包括在所选择的时间间隔内将结构选择性地暴露于等离子体。 曝光时间间隔的持续时间足以减少结构的极化，由此由偏振引起的力不会干扰被处理的晶片的传输或移动。

公开(公告)号：US06630677B1

公开(公告)日：2003-10-07

申请号：US09943570

申请日：2001-08-29

Applicant: Zhiyong Zhao ,  David Hendrix

Inventor： Zhiyong Zhao ,  David Hendrix

IPC: H01J3712

CPC classification number: H01J37/12 ,  H01J37/3171

Abstract: An electrostatic lens with glassy graphite electrodes for use in an ion implanter is disclosed. The graphite electrodes have been manufactured to be substantially smooth (glassy) such that irregularities on the surface grain of the graphite, for example peaks or apexes, are no longer present. In an embodiment, employing polished graphite electrostatic lens electrodes does not require the time-consuming conditioning operations under vacuum that are typically needed with conventional graphite electrodes, and thus offers the advantage of increased uptime for an ion implantation system. In addition, because surface irregularities are not present to serve as discharge points for electrostatic buildup, the use of glassy graphite electrodes as disclosed offers the advantage of electrostatic discharge reduction. Reduction of electrostatic discharge results in decreased particulate contamination from discharge events, as well as lessening of the probability of irreparable physical damage to implantation target material.

Abstract translation: 公开了一种用于离子注入机的具有玻璃状石墨电极的静电透镜。 石墨电极已被制造成基本上光滑（玻璃状），使得不再存在石墨表面晶粒上的凹凸，例如峰或顶点。 在一个实施例中，使用抛光的石墨静电透镜电极不需要在常规石墨电极通常需要的真空下的耗时的调节操作，因此提供了离子注入系统的正常运行时间增加的优点。 此外，由于不存在表面不规则性以用作静电积聚的放电点，因此所公开的玻璃状石墨电极的使用提供了静电放电还原的优点。 静电放电的减少导致放电事件引起的颗粒污染减少，以及降低对植入靶材料的不可挽回的物理损伤的可能性。

公开(公告)号：US08530961B2

公开(公告)日：2013-09-10

申请号：US13384002

申请日：2010-10-26

Applicant: Linchun Gui ,  Le Wang ,  Zhiyong Zhao ,  Lili He

Inventor： Linchun Gui ,  Le Wang ,  Zhiyong Zhao ,  Lili He

IPC: H01L29/66 ,  H01L21/336

CPC classification number: H01L29/66712 ,  H01L21/823418 ,  H01L21/823487 ,  H01L21/8249 ,  H01L27/088 ,  H01L29/0847 ,  H01L29/42368 ,  H01L29/66659 ,  H01L29/7809 ,  H01L29/7835

Abstract: A method for manufacturing compatible vertical double diffused metal oxide semiconductor (VDMOS) transistor and lateral double diffused metal oxide semiconductor (LDMOS) transistor includes: providing a substrate having an LDMOS transistor region and a VDMOS transistor region; forming an N-buried region in the substrate; forming an epitaxial layer on the N-buried layer region; forming isolation regions in the LDMOS transistor region and the VDMOS transistor region; forming a drift region in the LDMOS transistor region; forming gates in the LDMOS transistor region and the VDMOS transistor region; forming PBODY regions in the LDMOS transistor region and the VDMOS transistor region; forming an N-type GRADE region in the LDMOS transistor region; forming an NSINK region in the VDMOS transistor region, where the NSINK region is in contact with the N-buried layer region; forming sources and drains in the LDMOS transistor region and the VDMOS transistor region; and forming a P+ region in the LDMOS transistor region, where the P+ region is in contact with the source.

Abstract translation: 制造兼容的垂直双扩散金属氧化物半导体（VDMOS）晶体管和横向双扩散金属氧化物半导体（LDMOS）晶体管的方法包括：提供具有LDMOS晶体管区域和VDMOS晶体管区域的衬底; 在所述衬底中形成N掩埋区域; 在N掩埋层区域上形成外延层; 在LDMOS晶体管区域和VDMOS晶体管区域中形成隔离区域; 在LDMOS晶体管区域中形成漂移区; 在LDMOS晶体管区域和VDMOS晶体管区域中形成栅极; 在LDMOS晶体管区域和VDMOS晶体管区域中形成PBODY区域; 在LDMOS晶体管区域中形成N型GRADE区域; 在所述VDMOS晶体管区域中形成NSINK区域，其中所述NSINK区域与所述N埋层区域接触; 在LDMOS晶体管区域和VDMOS晶体管区域中形成源极和漏极; 以及在LDMOS晶体管区域中形成P +区域，其中P +区域与源极接触。

公开(公告)号：US20130001747A1

公开(公告)日：2013-01-03

申请号：US13519252

申请日：2010-12-02

Applicant: Le Wang ,  Linchun Gui ,  Kongwei Zhu ,  Zhiyong Zhao

Inventor： Le Wang ,  Linchun Gui ,  Kongwei Zhu ,  Zhiyong Zhao

IPC: H01L21/331 ,  H01L29/732

CPC classification number: H01L29/66272

Abstract: A method for manufacturing a bipolar transistor includes forming a first epitaxial layer on a semiconductor substrate, forming a second epitaxial layer on the first epitaxial layer, forming an oxide layer on the second epitaxial layer, etching the oxide layer to form an opening in which the second epitaxial layer is exposed, and forming a third epitaxial layer in the opening. The first and third epitaxial layers have a first-type conductivity, and the second epitaxial layer has a second-type conductivity.

Abstract translation: 一种用于制造双极晶体管的方法，包括在半导体衬底上形成第一外延层，在第一外延层上形成第二外延层，在第二外延层上形成氧化层，蚀刻氧化物层以形成开口， 暴露第二外延层，并在开口中形成第三外延层。 第一和第三外延层具有第一类型的导电性，第二外延层具有第二类型的导电性。

公开(公告)号：US08729669B2

公开(公告)日：2014-05-20

申请号：US13519252

申请日：2010-12-02

Applicant: Le Wang ,  Linchun Gui ,  Kongwei Zhu ,  Zhiyong Zhao

Inventor： Le Wang ,  Linchun Gui ,  Kongwei Zhu ,  Zhiyong Zhao

IPC: H01L29/02

CPC classification number: H01L29/66272

Abstract: A method for manufacturing a bipolar transistor includes forming a first epitaxial layer on a semiconductor substrate, forming a second epitaxial layer on the first epitaxial layer, forming an oxide layer on the second epitaxial layer, etching the oxide layer to form an opening in which the second epitaxial layer is exposed, and forming a third epitaxial layer in the opening. The first and third epitaxial layers have a first-type conductivity, and the second epitaxial layer has a second-type conductivity.

Abstract translation: 一种用于制造双极晶体管的方法，包括在半导体衬底上形成第一外延层，在第一外延层上形成第二外延层，在第二外延层上形成氧化层，蚀刻氧化物层以形成开口， 暴露第二外延层，并在开口中形成第三外延层。 第一和第三外延层具有第一类型的导电性，第二外延层具有第二类型的导电性。

公开(公告)号：US20120256252A1

公开(公告)日：2012-10-11

申请号：US13384002

申请日：2010-10-26

Applicant: Linchun Gui ,  Le Wang ,  Zhiyong Zhao ,  Lili He

Inventor： Linchun Gui ,  Le Wang ,  Zhiyong Zhao ,  Lili He

IPC: H01L29/78 ,  H01L21/8238

CPC classification number: H01L29/66712 ,  H01L21/823418 ,  H01L21/823487 ,  H01L21/8249 ,  H01L27/088 ,  H01L29/0847 ,  H01L29/42368 ,  H01L29/66659 ,  H01L29/7809 ,  H01L29/7835

Abstract: A method for manufacturing compatible vertical double diffused metal oxide semiconductor (VDMOS) transistor and lateral double diffused metal oxide semiconductor (LDMOS) transistor includes: providing a substrate having an LDMOS transistor region and a VDMOS transistor region; forming an N-buried region in the substrate; forming an epitaxial layer on the N-buried layer region; forming isolation regions in the LDMOS transistor region and the VDMOS transistor region; forming a drift region in the LDMOS transistor region; forming gates in the LDMOS transistor region and the VDMOS transistor region; forming PBODY regions in the LDMOS transistor region and the VDMOS transistor region; forming an N-type GRADE region in the LDMOS transistor region; forming an NSINK region in the VDMOS transistor region, where the NSINK region is in contact with the N-buried layer region; forming sources and drains in the LDMOS transistor region and the VDMOS transistor region; and forming a P+ region in the LDMOS transistor region, where the P+ region is in contact with the source.

Abstract translation: 制造兼容的垂直双扩散金属氧化物半导体（VDMOS）晶体管和横向双扩散金属氧化物半导体（LDMOS）晶体管的方法包括：提供具有LDMOS晶体管区域和VDMOS晶体管区域的衬底; 在所述衬底中形成N掩埋区域; 在N掩埋层区域上形成外延层; 在LDMOS晶体管区域和VDMOS晶体管区域中形成隔离区域; 在LDMOS晶体管区域中形成漂移区; 在LDMOS晶体管区域和VDMOS晶体管区域中形成栅极; 在LDMOS晶体管区域和VDMOS晶体管区域中形成PBODY区域; 在LDMOS晶体管区域中形成N型GRADE区域; 在所述VDMOS晶体管区域中形成NSINK区域，其中所述NSINK区域与所述N埋层区域接触; 在LDMOS晶体管区域和VDMOS晶体管区域中形成源极和漏极; 以及在LDMOS晶体管区域中形成P +区域，其中P +区域与源极接触。

公开(公告)号：US07063991B1

公开(公告)日：2006-06-20

申请号：US10900832

申请日：2004-07-28

Applicant: Zhiyong Zhao ,  Christian Krueger

Inventor： Zhiyong Zhao ,  Christian Krueger

IPC: H01L21/66 ,  G01R31/26

CPC classification number: G01R31/2831 ,  H01L21/26513

Abstract: Disclosed herein are various methods of determining characteristics of doped regions on device wafers, and a system for accomplishing same. In one illustrative embodiment, the method includes providing a device substrate comprising a plurality of masked areas, a plurality of unmasked areas, and at least one doped region formed in the substrate, determining a ratio between the unmasked areas and the masked areas for the device substrate, illuminating an area of the device substrate comprising the masked areas, the unmasked areas, and at least one doped region, and measuring an induced surface photovoltage of the device substrate while accounting for the ratio of the unmasked areas and the masked areas of the device substrate. In another illustrative embodiment, the method includes providing an SOI substrate comprised of an active layer, the active layer having a thickness, illuminating an area of the substrate using a light source having a wavelength that is sufficiently long such that an excited region created in the active layer due to the illumination does not extend beyond the thickness of the active layer, and measuring an induced surface photovoltage resulting from the illumination.

公开(公告)号：US08828924B2

公开(公告)日：2014-09-09

申请号：US12779935

申请日：2010-05-13

Applicant: E. Albert Reece ,  Zhiyong Zhao ,  Peixin Yang

Inventor： E. Albert Reece ,  Zhiyong Zhao ,  Peixin Yang

IPC: A61K38/00 ,  A61K31/5377 ,  A61K31/415 ,  A61K31/4545 ,  A61K38/18 ,  A61K38/44 ,  A61K31/506 ,  A61K31/40 ,  A61K31/445 ,  A61K39/00

CPC classification number: A61K31/40 ,  A61K31/415 ,  A61K31/445 ,  A61K31/4545 ,  A61K31/506 ,  A61K31/5377 ,  A61K38/1808 ,  A61K38/1825 ,  A61K38/44 ,  A61K2039/505 ,  C12Y103/01024

Abstract: Maternal diabetes can lead to a developmental malformation of an embryo. A developmental malformation caused by maternal diabetes is commonly referred to as a diabetic embryopathy. There is currently no effective treatment for reducing or inhibiting a diabetic embryopathy. To this end, the present invention is drawn to novel methods of treating a diabetic embryopathy.

Abstract translation: 产妇糖尿病可导致胚胎发育畸形。 由母亲糖尿病引起的发育畸形通常称为糖尿病性胚胎病。 目前没有有效的治疗减少或抑制糖尿病性胚胎病。 为此，本发明涉及治疗糖尿病性胚胎病的新方法。

公开(公告)号：US20090134953A1

公开(公告)日：2009-05-28

申请号：US12300464

申请日：2007-05-17

Applicant: Andrew Tye Hunt ,  Zhiyong Zhao ,  Yongdong Jiang ,  Xiaoyan Wang ,  Kwang Choi

Inventor： Andrew Tye Hunt ,  Zhiyong Zhao ,  Yongdong Jiang ,  Xiaoyan Wang ,  Kwang Choi

IPC: H03H7/01

CPC classification number: H01P1/184 ,  H01P1/203

Abstract: Tunable radio frequency (RF) devices, such as phase shifters and filters, are formed by depositing thin film layers on a substrate and patterning the thin film layers by various lithography techniques. A thin film metal layer is patterned to form a plurality of capacitors and inductors, leaving at least two grounding regions that lie closely adjacent the capacitors and inductors. As patterned portions of the grounding regions are electrically isolated from each other. Performance of the devices are improved by electrically bridging the differential potential grounding regions.

Abstract translation: 通过在衬底上沉积薄膜层并通过各种光刻技术对薄膜层进行图案化来形成可调谐射频（RF）器件，例如移相器和滤波器。 图案化薄膜金属层以形成多个电容器和电感器，留下紧邻电容器和电感器的至少两个接地区域。 由于接地区域的图案部分彼此电隔离。 通过电气桥接差分电位接地区来改善器件的性能。

公开(公告)号：US06797967B1

公开(公告)日：2004-09-28

申请号：US10082567

申请日：2002-02-25

Applicant: Tom Tse ,  Zhiyong Zhao ,  David M. Hendrix

Inventor： Tom Tse ,  Zhiyong Zhao ,  David M. Hendrix

IPC: G21K500

CPC classification number: H01J37/3171 ,  H01J2237/31703

Abstract: A method is presented for compensating for the effects of charge neutralization in calculating the ‘true’ ion dose, i.e., the dose assuming no changes of charge state of ions during an implantation process. An ion beam is generated under normal operating conditions, e.g., stable vacuum exists, and no target is being implanted. At least one additional detector would be positioned in the target chamber, and a dose measurement conducted simultaneously with a measurement of the beam current with the Faraday, which is located outside of the charge neutralization region, to establish a reference ratio. A wafer is then placed at the target location, and simultaneous measurements made with the additional detector and Faraday, as before, to determine the ratio between the beam current and the detector during wafer implantation. Any drift from the reference ratio indicates the dose error due to charge neutralization from wafer outgassing during implantation. Software for controlling various parameters could be configured to use the ratio drift data to change the dose counter to compensate for the dose error due to charge neutralization.

Abstract translation: 提出了一种用于补偿电荷中和在计算“真实”离子剂量时的影响的方法，即假定在注入过程中离子的电荷状态没有变化的剂量。 在正常操作条件下产生离子束，例如存在稳定的真空，并且不会植入靶。 至少一个额外的检测器将被定位在目标腔室中，并且与位于电荷中和区域外侧的法拉第的射束电流的测量同时进行剂量测量，以建立参考比。 然后将晶片放置在目标位置，并且如前所述使用附加检测器和法拉第进行的同时测量来确定在晶片植入期间束电流和检测器之间的比率。 参考比值的任何偏差表示由植入过程中的晶片放气引起的电荷中和引起的剂量误差。 用于控制各种参数的软件可以配置为使用比率漂移数据来改变剂量计数器，以补偿由于电荷中和引起的剂量误差。