公开(公告)号：US08044455B2

公开(公告)日：2011-10-25

申请号：US12683935

申请日：2010-01-07

Applicant: Yutaka Okuyama ,  Tsuyoshi Arigane

Inventor： Yutaka Okuyama ,  Tsuyoshi Arigane

IPC: H01L29/792

CPC classification number: H01L21/28282 ,  H01L27/11529 ,  H01L27/11565 ,  H01L27/11568

Abstract: A step is provided between a substrate surface of a select gate and a substrate surface of a memory gate. When the substrate surface of the select gate is lower than the substrate surface of the memory gate, electrons in a channel upon writing obliquely flow in the step portion. Even if the electrons obtain the energy required for passing a barrier during the oblique flow, the electron injection does not occur because electrons are away from the substrate surface. The injection can occur only on a drain region side from a position where the electrons reach the substrate surface. As a result, the injection of the electrons into a gap region is suppressed, so that the electron distribution comes close to the hole distribution. Therefore, variation in a threshold value upon information retention is suppressed, and information-retaining characteristics of a memory cell are improved.

Abstract translation: 在选择栅极的衬底表面和存储栅极的衬底表面之间提供一个步骤。 当选择栅极的衬底表面低于存储栅极的衬底表面时，写入中的通道中的电子在阶跃部分中倾斜地流动。 即使电子获得在斜流期间通过势垒所需的能量，电子注入也不会发生，因为电子远离衬底表面。 注入只能在电子到达基板表面的位置的漏极区域侧发生。 结果，电子注入到间隙区域被抑制，使得电子分布接近孔分布。 因此，抑制信息保持时的阈值的变化，提高存储单元的信息保持特性。

公开(公告)号：US20100193856A1

公开(公告)日：2010-08-05

申请号：US12683935

申请日：2010-01-07

Applicant: Yutaka Okuyama ,  Tsuyoshi Arigane

Inventor： Yutaka Okuyama ,  Tsuyoshi Arigane

IPC: H01L27/115 ,  H01L21/8246

CPC classification number: H01L21/28282 ,  H01L27/11529 ,  H01L27/11565 ,  H01L27/11568

Abstract: A step is provided between a substrate surface of a select gate and a substrate surface of a memory gate. When the substrate surface of the select gate is lower than the substrate surface of the memory gate, electrons in a channel upon writing obliquely flow in the step portion. Even if the electrons obtain the energy required for passing a barrier during the oblique flow, the electron injection does not occur because electrons are away from the substrate surface. The injection can occur only on a drain region side from a position where the electrons reach the substrate surface. As a result, the injection of the electrons into a gap region is suppressed, so that the electron distribution comes close to the hole distribution. Therefore, variation in a threshold value upon information retention is suppressed, and information-retaining characteristics of a memory cell are improved.

Abstract translation: 在选择栅极的衬底表面和存储栅极的衬底表面之间提供一个步骤。 当选择栅极的衬底表面低于存储栅极的衬底表面时，写入中的通道中的电子在阶跃部分中倾斜地流动。 即使电子获得在斜流期间通过势垒所需的能量，电子注入也不会发生，因为电子远离衬底表面。 注入只能在电子到达基板表面的位置的漏极区域侧发生。 结果，电子注入到间隙区域被抑制，使得电子分布接近孔分布。 因此，抑制信息保持时的阈值的变化，提高存储单元的信息保持特性。

公开(公告)号：US08385124B2

公开(公告)日：2013-02-26

申请号：US13075169

申请日：2011-03-29

Applicant: Tsuyoshi Arigane ,  Digh Hisamoto ,  Yasuhiro Shimamoto ,  Yutaka Okuyama

Inventor： Tsuyoshi Arigane ,  Digh Hisamoto ,  Yasuhiro Shimamoto ,  Yutaka Okuyama

IPC: G11C16/04

CPC classification number: H01L21/28282 ,  G11C16/0466 ,  H01L27/11573 ,  H01L29/42344 ,  H01L29/66833 ,  H01L29/78 ,  H01L29/792

Abstract: The semiconductor device includes the nonvolatile memory cell in the main surface of a semiconductor substrate. The nonvolatile memory cell has a first insulating film over the semiconductor substrate, a conductive film, a second insulating film, the charge storage film capable of storing therein charges, a third insulating film over the charge storage film, a first gate electrode, a fourth insulating film in contact with the set of stacked films from the first insulating film to the foregoing first gate electrode, a fifth insulating film juxtaposed with the first insulating film over the foregoing semiconductor substrate, a second gate electrode formed over the fifth insulating film to be adjacent to the foregoing first gate electrode over the side surface of the fourth insulating film, and source/drain regions with the first and second gate electrodes interposed therebetween. The conductive film and the charge storage film are formed to two-dimensionally overlap.

Abstract translation: 半导体器件包括在半导体衬底的主表面中的非易失性存储单元。 非易失性存储单元在半导体衬底上具有第一绝缘膜，导电膜，第二绝缘膜，能够存储电荷的电荷存储膜，电荷存储膜上的第三绝缘膜，第一栅电极，第四绝缘膜 绝缘膜与从第一绝缘膜到前述第一栅电极的层叠膜接触;第五绝缘膜，与上述半导体衬底上的第一绝缘膜并置，形成在第五绝缘膜上的第二栅电极， 与第四绝缘膜的侧表面上的上述第一栅电极相邻，以及其间插入第一和第二栅电极的源/漏区。 导电膜和电荷存储膜形成为二维重叠。

公开(公告)号：US20110235419A1

公开(公告)日：2011-09-29

申请号：US13073988

申请日：2011-03-28

Applicant: Tetsuya ISHIMARU ,  Yasuhiro Shimamoto ,  Hideo Kasai ,  Yutaka Okuyama ,  Tsuyoshi Arigane

Inventor： Tetsuya ISHIMARU ,  Yasuhiro Shimamoto ,  Hideo Kasai ,  Yutaka Okuyama ,  Tsuyoshi Arigane

IPC: G11C16/04

CPC classification number: G11C16/10 ,  G11C16/0466 ,  G11C16/14 ,  G11C16/30 ,  H01L27/11563 ,  H01L29/42344

Abstract: In a split gate MONOS memory which carries out rewrite by hot carrier injection, retention characteristics are improved. A select gate electrode of a memory cell is connected to a select gate line, and a memory gate electrode is connected to a memory gate line. A drain region is connected to a bit line, and a source region is connected to a source line. Furthermore, a well line is connected to a p type well region in which the memory cell is formed. When write to the memory cell is to be carried out, write by a source side injection method is carried out while applying a negative voltage to the p type well region via the well line.

Abstract translation: 在通过热载流子注入进行重写的分闸门MONOS存储器中，保持特性得到改善。 存储单元的选择栅电极连接到选择栅极线，并且存储栅电极连接到存储栅极线。 漏极区域连接到位线，并且源极区域连接到源极线。 此外，阱线连接到其中形成存储单元的p型阱区域。 当要对存储单元进行写入时，通过源极侧注入方法进行写入，同时通过阱线向p型阱区域施加负电压。

公开(公告)号：US20080025107A1

公开(公告)日：2008-01-31

申请号：US11822120

申请日：2007-07-02

Applicant: Tetsufumi Kawamura ,  Hitoshi Kume ,  Tsuyoshi Arigane

Inventor： Tetsufumi Kawamura ,  Hitoshi Kume ,  Tsuyoshi Arigane

IPC: G11C11/34 ,  G11C16/04

CPC classification number: G11C16/0416 ,  G11C16/0425 ,  G11C16/0433 ,  G11C16/0458 ,  G11C16/0491 ,  G11C16/3427 ,  H01L27/105 ,  H01L27/11526 ,  H01L27/11529 ,  H01L27/11568

Abstract: A highly-reliable semiconductor device is realized. For example, each memory cell of a nonvolatile memory included in the semiconductor device is configured to include a source and a drain formed in a P-well, a memory node which is formed on the P-well between the source and the drain via a tunnel insulator and is insulated from its periphery, and a control gate formed on the memory node via an interlayer insulator. When a programming operation using channel hot electrons is to be performed in such a configuration, the P-well is put into an electrically floating state.

Abstract translation: 实现了高可靠性的半导体器件。 例如，包括在半导体器件中的非易失性存储器的每个存储单元被配置为包括形成在P阱中的源极和漏极，存储器节点，其通过经由一个或多个源极和漏极形成在源极和漏极之间的P阱上 隧道绝缘子，并与其周边绝缘，以及通过层间绝缘体形成在存储节点上的控制栅极。 当以这种结构执行使用通道热电子的编程操作时，P阱被置于电浮置状态。

公开(公告)号：US08409949B2

公开(公告)日：2013-04-02

申请号：US12822157

申请日：2010-06-23

Applicant: Tsuyoshi Arigane ,  Digh Hisamoto ,  Yasuhiro Shimamoto ,  Toshiyuki Mine

Inventor： Tsuyoshi Arigane ,  Digh Hisamoto ,  Yasuhiro Shimamoto ,  Toshiyuki Mine

IPC: H01L21/336

CPC classification number: H01L29/42328 ,  G11C16/3418 ,  H01L27/11521 ,  H01L27/1203 ,  H01L29/7883

Abstract: Provided is a nonvolatile semiconductor memory device highly integrated and highly reliable. A plurality of memory cells are formed in a plurality of active regions sectioned by a plurality of isolations (silicon oxide films) extending in the Y direction and deeper than a well (p type semiconductor region). In each memory cell, a contact is provided in the well (p type semiconductor region) so as to penetrate through a source diffusion layer (n+ type semiconductor region), and the contact that electrically connects bit lines (metal wirings) and the source diffusion layer (n+ type semiconductor region) is also electrically connected to the well (p type semiconductor region).

Abstract translation: 提供了高度集成且高度可靠的非易失性半导体存储器件。 多个存储单元形成在由在Y方向上延伸并且比阱（p型半导体区域）更深的多个隔离（氧化硅膜）分割的多个有源区域中。 在每个存储单元中，在阱（p型半导体区域）中提供接触以穿透源极扩散层（n +型半导体区域），并且将位线（金属布线）和源极扩散 层（n +型半导体区）也与阱（p型半导体区）电连接。

公开(公告)号：US20060183284A1

公开(公告)日：2006-08-17

申请号：US11316817

申请日：2005-12-27

Applicant: Yoshitaka Sasago ,  Tsuyoshi Arigane ,  Tetsufumi Kawamura ,  Hitoshi Kume ,  Takashi Kobayashi

Inventor： Yoshitaka Sasago ,  Tsuyoshi Arigane ,  Tetsufumi Kawamura ,  Hitoshi Kume ,  Takashi Kobayashi

IPC: H01L21/336

CPC classification number: G11C16/0491 ,  G11C16/0433 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11526 ,  H01L27/11546 ,  H01L29/40114

Abstract: High integration and making a non-volatile semiconductor memory efficient have been promoted. The memory cell consists of a floating gate, a control gate constituting a word line WL and a MOS transistor having an assist gate. The thickness of the gate oxide film of the assist gate is thinner than the thickness of the gate oxide layer of the floating gate, and the dimensions of the assist gate (gate width) in the direction lying along the word line WL is smaller than the gate length of the floating gate in the direction lying along the word line WL. Moreover, the channel dopant concentration underneath the assist gate is lower than the channel dopant concentration underneath the floating gate.

Abstract translation: 高集成度和非易失性半导体存储器的高效率得到了提升。 存储单元包括浮置栅极，构成字线WL的控制栅极和具有辅助栅极的MOS晶体管。 辅助栅极的栅极氧化膜的厚度比浮栅的栅极氧化物层的厚度薄，并且沿着字线WL的方向上的辅助栅极（栅极宽度）的尺寸小于 浮栅的沿着字线WL的方向的栅极长度。 此外，辅助栅极下方的沟道掺杂剂浓度低于浮栅下方的沟道掺杂剂浓度。

公开(公告)号：US08796756B2

公开(公告)日：2014-08-05

申请号：US13755348

申请日：2013-01-31

Applicant: Kenichi Akita ,  Daisuke Okada ,  Keisuke Kuwahara ,  Yasafumi Morimoto ,  Yasuhiro Shimamoto ,  Kan Yasui ,  Tsuyoshi Arigane ,  Tetsuya Ishimaru

Inventor： Kenichi Akita ,  Daisuke Okada ,  Keisuke Kuwahara ,  Yasafumi Morimoto ,  Yasuhiro Shimamoto ,  Kan Yasui ,  Tsuyoshi Arigane ,  Tetsuya Ishimaru

IPC: H01L29/792

CPC classification number: H01L29/66833 ,  H01L27/115 ,  H01L27/11563 ,  H01L27/11568 ,  H01L29/792

Abstract: A charge storage layer interposed between a memory gate electrode and a semiconductor substrate is formed shorter than a gate length of the memory gate electrode or a length of insulating films so as to make the overlapping amount of the charge storage layer and a source region to be less than 40 nm. Therefore, in the write state, since the movement in the transverse direction of the electrons and the holes locally existing in the charge storage layer decreases, the variation of the threshold voltage when holding a high temperature can be reduced. In addition, the effective channel length is made to be 30 nm or less so as to reduce an apparent amount of holes so that coupling of the electrons with the holes in the charge storage layer decreases; therefore, the variation of the threshold voltage when holding at room temperature can be reduced.

Abstract translation: 插入在存储栅电极和半导体衬底之间的电荷存储层形成为比存储栅电极的栅极长度或绝缘膜的长度短，以使电荷存储层和源极区域的重叠量成为 小于40nm。 因此，在写入状态下，由于在电荷存储层中局部存在的电子和空穴的横向的移动减少，因此可以降低保持高温时的阈值电压的变化。 此外，有效沟道长度为30nm以下，以减少空穴的表观量，使得电子与电荷存储层中的空穴的耦合减小; 因此，可以降低在室温下保持时的阈值电压的变化。

公开(公告)号：US20090134449A1

公开(公告)日：2009-05-28

申请号：US12273308

申请日：2008-11-18

Applicant: Tsuyoshi Arigane ,  Digh Hisamoto ,  Yasuhiro Shimamoto ,  Toshiyuki Mine

Inventor： Tsuyoshi Arigane ,  Digh Hisamoto ,  Yasuhiro Shimamoto ,  Toshiyuki Mine

IPC: H01L29/792 ,  H01L21/336

CPC classification number: H01L29/42328 ,  G11C16/3418 ,  H01L27/11521 ,  H01L27/1203 ,  H01L29/7883

Abstract: Provided is a nonvolatile semiconductor memory device highly integrated and highly reliable. A plurality of memory cells are formed in a plurality of active regions sectioned by a plurality of isolations (silicon oxide films) extending in the Y direction and deeper than a well (p type semiconductor region). In each memory cell, a contact is provided in the well (p type semiconductor region) so as to penetrate through a source diffusion layer (n+ type semiconductor region), and the contact that electrically connects bit lines (metal wirings) and the source diffusion layer (n+ type semiconductor region) is also electrically connected to the well (p type semiconductor region).

Abstract translation: 提供了高度集成且高度可靠的非易失性半导体存储器件。 多个存储单元形成在由在Y方向上延伸并且比阱（p型半导体区域）更深的多个隔离（氧化硅膜）分割的多个有源区域中。 在每个存储单元中，在阱（p型半导体区域）中提供接触以穿透源极扩散层（n +型半导体区域），并且将位线（金属布线）和源极扩散 层（n +型半导体区）也与阱（p型半导体区）电连接。

公开(公告)号：US07411242B2

公开(公告)日：2008-08-12

申请号：US11239338

申请日：2005-09-30

Applicant: Takashi Kobayashi ,  Yoshitaka Sasago ,  Tsuyoshi Arigane ,  Yoshihiro Ikeda ,  Kenji Kanamitsu

Inventor： Takashi Kobayashi ,  Yoshitaka Sasago ,  Tsuyoshi Arigane ,  Yoshihiro Ikeda ,  Kenji Kanamitsu

IPC: H01L29/76

CPC classification number: H01L27/11526 ,  G11C16/0491 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11546 ,  H01L29/42324

Abstract: The object of the present invention is to provide a new nonvolatile semiconductor memory device and its manufacturing method for the purpose of miniaturizing a virtual grounding type memory cell based on a three-layer polysilicon gate, enhancing the performance, and boosting the yield. In a memory cell according to the present invention, a floating gate's two end faces perpendicular to a word line and channel are partly placed over the top of a third gate via a dielectric film. The present invention can reduce the memory cell area of a nonvolatile semiconductor memory device, increase the operating speed, and enhances the yield.

Abstract translation: 本发明的目的是提供一种新的非易失性半导体存储器件及其制造方法，其目的是使三层多晶硅栅极的虚拟接地型存储单元小型化，提高性能，提高产量。 在根据本发明的存储器单元中，垂直于字线和沟道的浮动栅极的两个端面部分地通过电介质膜放置在第三栅极的顶部上。 本发明可以减少非易失性半导体存储器件的存储单元面积，提高工作速度，提高产量。