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    Apparatus and method to improve uniformity and reduce local effect of process chamber
    1.
    发明授权
    Apparatus and method to improve uniformity and reduce local effect of process chamber 有权
    提高加工室均匀性和降低局部效果的装置和方法

    公开(公告)号：US08223470B2

    公开(公告)日：2012-07-17

    申请号：US11539958

    申请日：2006-10-10

    Applicant: Yu-Cheng Chang ,  Ying-Lin Chen

    Inventor： Yu-Cheng Chang ,  Ying-Lin Chen

    IPC: H01T23/00

    CPC classification number: H01L21/68764 ,  H01J37/321 ,  H01J37/32568 ,  H01L21/67069

    Abstract: An apparatus includes a processing chamber having a plasma containing region, a dielectric plate secured on top of the processing chamber, a power source separated from the plasma containing region by the dielectric plate, and a chuck supported within the processing chamber. The chuck is operable and configured to move with respect to the power source.

    Abstract translation: 一种装置包括具有等离子体容纳区域的处理室，固定在处理室顶部的电介质板，通过电介质板与等离子体容纳区域分离的电源，以及支撑在处理室内的卡盘。 卡盘可操作和配置成相对于电源移动。

    Row-identifier list processing management
    2.
    发明授权
    Row-identifier list processing management 失效
    行标识列表处理管理

    公开(公告)号：US07895185B2

    公开(公告)日：2011-02-22

    申请号：US11536400

    申请日：2006-09-28

    Applicant: Ying-Lin Chen ,  You-Chin Fuh ,  Fen-Ling Lin ,  Terence Patrick Purcell ,  Ying Zeng

    Inventor： Ying-Lin Chen ,  You-Chin Fuh ,  Fen-Ling Lin ,  Terence Patrick Purcell ,  Ying Zeng

    IPC: G06F17/30

    CPC classification number: G06F17/30492 ,  G06F17/30321

    Abstract: A method, computer program product, and system for managing row identifier (RID) list processing on an index are provided. The method, computer program product, and system provide for accessing one or more key values in the index based on one or more keys specified in a query, retrieving a plurality of row identifiers corresponding to the one or more key values from the index, and predicting an actual number of row identifiers to be retrieved from the index based on the one or more key values accessed and the plurality of row identifiers retrieved.

    Abstract translation: 提供了一种用于管理索引上的行标识符（RID）列表处理的方法，计算机程序产品和系统。 该方法，计算机程序产品和系统提供了基于查询中指定的一个或多个键访问索引中的一个或多个键值，从索引检索对应于一个或多个键值的多个行标识符，以及 基于所访问的一个或多个键值和检索的多个行标识符来预测要从索引检索的行标识符的实际数量。

    Approach to prevent undercut of oxide layer below gate spacer through nitridation
    4.
    发明授权
    Approach to prevent undercut of oxide layer below gate spacer through nitridation 有权
    通过氮化防止栅极隔离层下面的氧化层底切的方法

    公开(公告)号：US06916718B2

    公开(公告)日：2005-07-12

    申请号：US10613606

    申请日：2003-07-03

    Applicant: Ying-Lin Chen ,  Chiang-Lang Yen ,  Ling-Sung Wang

    Inventor： Ying-Lin Chen ,  Chiang-Lang Yen ,  Ling-Sung Wang

    IPC: H01L21/311 ,  H01L21/336

    CPC classification number: H01L29/665 ,  H01L21/31116 ,  H01L29/6656

    Abstract: A method is provided for the removal of liner oxide from the surface of a gate electrode during the creation of the gate electrode. A layer of gate oxide is formed over the surface of a substrate, a layer of gate electrode is deposited over the layer of gate oxide. The gate electrode is deposited, gate spacers are formed over the liner oxide, exposing surfaces of the liner oxide. The created structure is nitrided by a plasma stream containing N2/H2, reducing the etch rate of the exposed liner oxide. The liner oxide is then removed by applying a wet etch, contact regions to the gate electrode are salicided.

    Abstract translation: 提供了一种在栅极电极生成期间从栅电极的表面去除衬垫氧化物的方法。 在衬底的表面上形成栅极氧化物层，栅电极层沉积在栅极氧化物层上。 沉积栅电极，在衬垫氧化物上方形成栅极隔离物，暴露衬里氧化物的表面。 所产生的结构被含有N 2 / H 2 O 2的等离子体流渗氮，降低了暴露的衬垫氧化物的蚀刻速率。 然后通过施加湿蚀刻来除去衬里氧化物，对栅电极的接触区域进行浸蚀。

    Approach to prevent spacer undercut by low temperature nitridation
    5.
    发明授权
    Approach to prevent spacer undercut by low temperature nitridation 有权
    通过低温氮化防止间隔底切的方法

    公开(公告)号：US06610571B1

    公开(公告)日：2003-08-26

    申请号：US10068929

    申请日：2002-02-07

    Applicant: Ying-Lin Chen ,  Chiang-Lang Yen ,  Ling-Sung Wang

    Inventor： Ying-Lin Chen ,  Chiang-Lang Yen ,  Ling-Sung Wang

    IPC: H01L21336

    CPC classification number: H01L29/665 ,  H01L21/31116 ,  H01L29/6656

    Abstract: A new method is provided for the removal of liner oxide from the surface of a gate electrode during the creation of the gate electrode. A layer of gate oxide is formed over the surface of a substrate, a layer of gate electrode such as polyimide is deposited over the layer of gate oxide. The gate electrode and the layer of gate oxide are patterned. A layer of liner oxide is deposited, gate spacers are formed over the liner oxide, exposing surfaces of the liner oxide. The created structure is nitrided by a plasma stream containing N2/H2, reducing the etch rate of the exposed liner oxide. The liner oxide is then removed by applying a wet etch, contact regions to the gate electrode are salicided.

    Abstract translation: 提供了一种新的方法，用于在栅电极生成期间从栅电极的表面去除衬垫氧化物。 在衬底的表面上形成栅极氧化物层，在栅极氧化物层上沉积诸如聚酰亚胺的栅电极层。 栅极电极和栅极氧化物层被图案化。 沉积一层衬垫氧化物，在衬垫氧化物上形成栅极间隔物，暴露衬里氧化物的表面。 所产生的结构被含有N 2 / H 2的等离子体流渗氮，降低了暴露的衬垫氧化物的蚀刻速率。 然后通过施加湿蚀刻来除去衬里氧化物，对栅电极的接触区域进行浸蚀。

    Method of making a flexible printed circuit board
    6.
    发明授权
    Method of making a flexible printed circuit board 有权
    制造柔性印刷电路板的方法

    公开(公告)号：US07992290B2

    公开(公告)日：2011-08-09

    申请号：US11940900

    申请日：2007-11-15

    Applicant: Ying-Lin Chen ,  Yung-Chou Chen

    Inventor： Ying-Lin Chen ,  Yung-Chou Chen

    IPC: H05K3/36 ,  B32B3/10

    CPC classification number: H05K3/427 ,  H05K1/0393 ,  H05K1/181 ,  H05K3/4652 ,  H05K2201/0166 ,  H05K2201/043 ,  H05K2201/09536 ,  H05K2203/0264 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/4913 ,  Y10T29/49156 ,  Y10T29/49165 ,  Y10T156/1052 ,  Y10T428/24273

    Abstract: An exemplary method of making an FPC includes forming a substrate comprising metal foil layers interleaved with intervening layers by: (a) laminating intervening layers with metal foil layers; (b) adhering a covering film to outermost surfaces of the substrate; (c) defining a hole in one side of the substrate through the covering film and at least two metal foil layers and the intervening layer between the at least two metal foil layers by etching or laser technology; and (d) plating a portion of an inner wall of the hole with conductive material to form a via to electrically connect the at least two metal foil layers.

    Abstract translation: 制造FPC的示例性方法包括：通过以下步骤形成包含与中间层交错的金属箔层的基板：（a）将介入层与金属箔层层压; （b）将覆盖膜粘附到基板的最外表面; （c）通过蚀刻或激光技术通过覆盖膜和至少两个金属箔层和至少两个金属箔层之间的中间层来限定衬底的一侧中的孔; 以及（d）用导电材料电镀所述孔的内壁的一部分以形成通孔以电连接所述至少两个金属箔层。

    Camera module
    7.
    发明授权
    Camera module 有权
    相机模块

    公开(公告)号：US07929052B2

    公开(公告)日：2011-04-19

    申请号：US12061883

    申请日：2008-04-03

    Applicant: Ying-Lin Chen ,  Yung-Chou Chen ,  Wen-Chang Chen

    Inventor： Ying-Lin Chen ,  Yung-Chou Chen ,  Wen-Chang Chen

    IPC: H04N5/225

    CPC classification number: G02B7/02 ,  G03B17/12 ,  H04N5/2251 ,  H04N5/2257 ,  H05K1/183 ,  H05K2201/10121

    Abstract: A camera module includes a lens module, an image sensor, and a circuit board. The image sensor module is disposed in an image side of the lens module. The circuit board is electronically connected with the image sensor module. The circuit board includes a receiving chamber defined therein. The receiving chamber receives the image sensor module. The lens module is mounted on the circuit board and covers the receiving chamber. The image sensor module is fixed in the receiving chamber that is defined in the circuit board therein. Therefore, a thickness of the camera module along the axis of the camera module is decreased and a volume of the camera module becomes thinner compare with the conventional camera module.

    Abstract translation: 相机模块包括透镜模块，图像传感器和电路板。 图像传感器模块设置在透镜模块的图像侧。 电路板与图像传感器模块电连接。 电路板包括限定在其中的接收室。 接收室接收图像传感器模块。 透镜模块安装在电路板上并覆盖接收室。 图像传感器模块固定在电路板中限定的接收室中。 因此，相机模块沿相机模块的轴线的厚度减小，并且相机模块的体积相对于传统相机模块变薄。

    Process flow to reduce spacer undercut phenomena
    9.
    发明授权
    Process flow to reduce spacer undercut phenomena 有权
    工艺流程减少间隔底切现象

    公开(公告)号：US06448167B1

    公开(公告)日：2002-09-10

    申请号：US10027976

    申请日：2001-12-20

    Applicant: Ling-Sung Wang ,  Ying-Lin Chen

    Inventor： Ling-Sung Wang ,  Ying-Lin Chen

    IPC: H01L214763

    CPC classification number: H01L29/665 ,  H01L29/6656 ,  H01L29/6659

    Abstract: A process for forming a composite insulator spacer on the sides of a MOSFET gate structure, wherein the underlying component of the composite insulator spacer is comprised of a thin silicon oxide layer obtained via chemical vapor deposition procedures using tetraethylorthosilicate (TEOS), as a source, has been developed. To densify the underlying thin silicon oxide layer an anneal procedure usually performed after implantation of ions used for a lightly doped source/drain region, is delayed and performed after deposition of the thin silicon oxide layer. The anneal procedure is then used for both activation of the lightly doped source/drain ions, and densification of the thin silicon oxide layer. The etch rate of the densified silicon oxide layer, in dilute hydrofluoric acid procedures is now reduced allowing the underlying silicon oxide component, of the composite insulator spacer, to survive subsequent wet clean procedures employing dilute hydrofluoric acid.

    Abstract translation: 一种用于在MOSFET栅极结构的侧面上形成复合绝缘体间隔物的方法，其中复合绝缘体间隔物的下面的部件由通过使用四乙基原硅酸盐（TEOS）作为源的化学气相沉积方法获得的薄氧化硅层组成， 已经开发。 为了致密化下面的薄氧化硅层，通常在注入用于轻掺杂源/漏区的离子之后进行的退火工艺在沉积薄氧化硅层之后被延迟和执行。 然后退火过程用于轻掺杂源极/漏极离子的激活和薄氧化硅层的致密化。 在稀氢氟酸方法中，致密化的氧化硅层的蚀刻速率现在减少，允许复合绝缘体间隔物的下面的氧化硅组分在随后的使用稀氢氟酸的湿法清洁程序中存活。

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