公开(公告)号：US06180459B2

公开(公告)日：2001-01-30

申请号：US09227974

申请日：1999-01-08

Applicant: Yau-Kae Sheu

Inventor： Yau-Kae Sheu

IPC: H01L218247

CPC classification number: H01L27/11526 ,  H01L27/11521 ,  H01L27/11531

Abstract: A method for fabricating a flash memory is provided. The method contains sequentially forming a tunnel oxide layer, a first polysilicon layer, and a silicon nitride layer on a semiconductor substrate. A shallow trench isolation (STI) structure is formed in the substrate to define an active area. During the formation of the STI structure, the first polysilicon is simultaneously pre-patterned. The silicon nitride layer is removed. A dielectric layer and a second polysilicon layer are sequentially formed over the substrate. The second polysilicon layer, the dielectric layer, the first polysilicon layer, and the tunnel oxide layer are patterned to form a desired strip structure on the substrate. A remaining portion of the first polysilicon layer serves as a gate of a memory cell. An interchangeable source/drain region is formed by ion implantation at each side of the gate structure, in which a source line parallel to the strip remaining structure.

Abstract translation: 提供一种制造闪存的方法。 该方法包括在半导体衬底上依次形成隧道氧化物层，第一多晶硅层和氮化硅层。 在衬底中形成浅沟槽隔离（STI）结构以限定有源区。 在STI结构的形成期间，第一多晶硅同时被预先构图。 去除氮化硅层。 介电层和第二多晶硅层依次形成在衬底上。 图案化第二多晶硅层，电介质层，第一多晶硅层和隧道氧化物层，以在衬底上形成期望的带状结构。 第一多晶硅层的剩余部分用作存储单元的栅极。 通过离子注入在栅极结构的每一侧形成可互换的源极/漏极区域，其中源极线平行于带状残留结构。

公开(公告)号：US5872036A

公开(公告)日：1999-02-16

申请号：US998331

申请日：1997-12-24

Applicant: Yau-Kae Sheu

Inventor： Yau-Kae Sheu

IPC: H01L21/8247 ,  H01L21/336 ,  H01L27/115 ,  H01L29/423 ,  H01L29/788 ,  H01L29/792

CPC classification number: H01L29/66825 ,  H01L29/42324

Abstract: A split-gate flash memory cell structure comprising a semiconductor substrate having a gate oxide layer already formed thereon. A first gate is then formed over the gate oxide layer, and a cross-section of the first gate contains two corners, one of which is a sharp corner. An insulating dielectric layer is then formed over the first gate. The insulating dielectric has a lens-shaped cross-section located above the sharp corner. Next, a second gate is formed over the insulating dielectric layer, and surrounded the first gate. A first doped region is formed in the substrate below the sharp corner. Then, a second doped region is formed in the substrate located on the other side of the first gate just opposite the first doped region, furthermore, the second doped region is separated from the first gate by a distance. There is a channel region between the first doped region and the second doped region, and the sharp corner of this invention is located above the semiconductor substrate outside the channel region.

Abstract translation: 一种分离栅闪存单元结构，包括其上已经形成有栅氧化层的半导体衬底。 然后在栅极氧化物层上形成第一栅极，并且第一栅极的横截面包含两个角，其中一个角是尖角。 然后在第一栅极上形成绝缘介电层。 绝缘电介质具有位于尖角上方的透镜形横截面。 接下来，在绝缘介电层上形成第二栅极，并围绕第一栅极。 第一掺杂区域形成在尖锐角下方的衬底中。 然后，第二掺杂区域形成在位于第一栅极另一侧的衬底中，恰好与第一掺杂区域相对，此外，第二掺杂区域与第一栅极分离一定距离。 在第一掺杂区域和第二掺杂区域之间存在沟道区域，本发明的尖角位于沟道区域外部的半导体衬底的上方。

公开(公告)号：US08546226B2

公开(公告)日：2013-10-01

申请号：US13189632

申请日：2011-07-25

Applicant: Chih-Ming Wang ,  Ping-Chia Shih ,  Chun-Sung Huang ,  Chi-Cheng Huang ,  Hsiang-Chen Lee ,  Chih-Hung Lin ,  Yau-Kae Sheu

Inventor： Chih-Ming Wang ,  Ping-Chia Shih ,  Chun-Sung Huang ,  Chi-Cheng Huang ,  Hsiang-Chen Lee ,  Chih-Hung Lin ,  Yau-Kae Sheu

IPC: H01L21/336 ,  H01L29/792

CPC classification number: H01L21/28282 ,  H01L29/792

Abstract: A method for fabricating a silicon-oxide-nitride-oxide-silicon (SONOS) non-volatile memory cell, wherein the method comprises steps as following: a pad oxide layer and a first hard mask layer are sequentially formed on a substrate. The pad oxide layer and the first hard mask layer are then etched through to form an opening exposing a portion of the substrate. Subsequently, an oxide-nitride-oxide (ONO) structure with a size substantially less than or equal to the opening is formed to coincide with the portion of the substrate exposed from the opening.

Abstract translation: 一种用于制造氧化硅 - 氧化物 - 氧化物 - 硅（SONOS）非易失性存储单元的方法，其中该方法包括以下步骤：在衬底上依次形成衬垫氧化物层和第一硬掩模层。 然后将衬垫氧化物层和第一硬掩模层蚀刻通过以形成露出衬底的一部分的开口。 随后，形成具有基本上小于或等于该开口的尺寸的氧化物 - 氧化物 - 氧化物（ONO）结构，以与从该开口露出的该基板的一部分重合。

公开(公告)号：US6157057A

公开(公告)日：2000-12-05

申请号：US24782

申请日：1998-02-17

Applicant: Yau-Kae Sheu ,  Gary Hong

Inventor： Yau-Kae Sheu ,  Gary Hong

IPC: H01L21/336 ,  H01L29/788

CPC classification number: H01L29/66825 ,  H01L29/7885

Abstract: A flash memory cell. A heavily doped region with the opposite polarity of the drain region is formed between the channel region and the drain region. The heavily doped region is in a bar shape extending towards both the drain and the source regions along a side of the floating gate. Furthermore, the reading operation is performed in reverse by applying a zero voltage to the drain region, and a non-zero voltage to the source region.

Abstract translation: 闪存单元。 在沟道区域和漏极区域之间形成具有与漏极区域相反极性的重掺杂区域。 重掺杂区域是沿浮动栅极的一侧向漏极和源极区域延伸的棒状。 此外，通过向漏极区域施加零电压并且向源极区域施加非零电压来反向执行读取操作。

公开(公告)号：US5994185A

公开(公告)日：1999-11-30

申请号：US24163

申请日：1998-02-17

Applicant: Yau-Kae Sheu ,  Gary Hong

Inventor： Yau-Kae Sheu ,  Gary Hong

IPC: H01L21/336 ,  H01L29/788

CPC classification number: H01L29/66825 ,  H01L29/7885

Abstract: A method of fabricating a flash memory. A heavily doped region with the opposite polarity of the drain region is formed between the channel region and the drain region. The heavily doped region is in a bar shape extending towards both the drain and the source regions along a side of the floating gate. Furthermore, the reading operation is performed in reverse by applying a zero voltage to the drain region, and a non-zero voltage to the source region.

Abstract translation: 一种制造闪速存储器的方法。 在沟道区域和漏极区域之间形成具有与漏极区域相反极性的重掺杂区域。 重掺杂区域是沿浮动栅极的一侧向漏极和源极区域延伸的棒状。 此外，通过向漏极区域施加零电压并且向源极区域施加非零电压来反向执行读取操作。

公开(公告)号：US6051469A

公开(公告)日：2000-04-18

申请号：US082660

申请日：1998-05-21

Applicant: Yau-Kae Sheu ,  Gary Hong

Inventor： Yau-Kae Sheu ,  Gary Hong

IPC: H01L21/8246 ,  H01L21/336

CPC classification number: H01L27/1122

Abstract: A method of fabricating a bit line on a semiconductor substrate is provided. First, an oxide layer is formed and patterned on the substrate. An epitaxial layer is formed on the exposed substrate after patterning the oxide layer. A first spacer and a second spacer are sequentially formed on the sidewalls of a opening of the oxide layer. A trench is formed by partially removing the epitaxial layer and the substrate. A liner oxide layer is formed in the trench after removing the second spacer. A polysilicon layer as a conductive layer is formed in the trench after removing the first spacer. Then, a step of ion implantation and an annealing step are carried out. A buried bit line is formed after etching back the polysilicon layer.

Abstract translation: 提供一种在半导体衬底上制造位线的方法。 首先，在基板上形成氧化层并图案化。 在图案化氧化物层之后，在暴露的衬底上形成外延层。 第一间隔物和第二间隔物依次形成在氧化物层的开口的侧壁上。 通过部分去除外延层和衬底形成沟槽。 在去除第二间隔物之后，在沟槽中形成衬里氧化物层。 在除去第一间隔物之后，在沟槽中形成作为导电层的多晶硅层。 然后，进行离子注入和退火步骤。 在蚀刻多晶硅层之后形成掩埋位线。

公开(公告)号：US5856224A

公开(公告)日：1999-01-05

申请号：US46061

申请日：1998-03-23

Applicant: Yau-Kae Sheu

Inventor： Yau-Kae Sheu

IPC: H01L21/8247

CPC classification number: H01L27/11521

Abstract: A method of fabricating split-gate slash memory can define source and drain regions by using a self-alignment process. Thus, the uniformity of the split-gate flash memory performance is better controlled. This method comprises a floating gate oxide layer, a first polysilicon layer and a mask layer formed sequentially over a first type substrate. The mask layer and the first polysilicon layer are patterned to form a floating gate. A photoresist layer is coated over the substrate and then a pattern is defined on the photoresist layer to expose portion of the substrate. Second type ions are implanted into the exposed substrate to form a drain region. Then, the photoresist layer is removed. An insulating layer is formed over the substrate and then is etched back to form spacers on one side of the floating gate. The second type ions are implanted into the substrate to form a source region. The spacers and the mask layer are removed. A control gate layer and a control gate are formed sequentially over the substrate.

Abstract translation: 分离栅极存储器的制造方法可以通过使用自对准工艺来定义源极和漏极区域。 因此，更好地控制分闸门闪存性能的均匀性。 该方法包括在第一类型衬底上顺序形成的浮栅氧化层，第一多晶硅层和掩模层。 掩模层和第一多晶硅层被图案化以形成浮栅。 将光致抗蚀剂层涂覆在衬底上，然后在光致抗蚀剂层上限定图案以暴露衬底的部分。 将第二类型离子注入暴露的衬底中以形成漏区。 然后，除去光致抗蚀剂层。 绝缘层形成在衬底上，然后被回蚀刻以在浮动栅极的一侧上形成间隔物。 将第二种离子注入到衬底中以形成源区。 去除间隔物和掩模层。 在衬底上顺序地形成控制栅极层和控制栅极。

公开(公告)号：US08546871B2

公开(公告)日：2013-10-01

申请号：US13177520

申请日：2011-07-06

Applicant: Chi-Cheng Huang ,  Ping-Chia Shih ,  Chih-Ming Wang ,  Chun-Sung Huang ,  Hsiang-Chen Lee ,  Chih-Hung Lin ,  Yau-Kae Sheu

Inventor： Chi-Cheng Huang ,  Ping-Chia Shih ,  Chih-Ming Wang ,  Chun-Sung Huang ,  Hsiang-Chen Lee ,  Chih-Hung Lin ,  Yau-Kae Sheu

IPC: H01L29/792

CPC classification number: H01L29/7923 ,  H01L29/66833

Abstract: A non-volatile memory cell includes a substrate, two charge trapping structures, a gate oxide layer, a gate and two doping regions. The charge trapping structures are disposed on the substrate separately. The gate oxide layer is disposed on the substrate between the two charge trapping structures. The gate is disposed on the gate oxide layer and the charge trapping structures, wherein the charge trapping structures protrude from two sides of the gate. The doping regions are disposed in the substrate at two sides of the gate.

Abstract translation: 非易失性存储单元包括衬底，两个电荷俘获结构，栅极氧化层，栅极和两个掺杂区域。 电荷捕获结构分别设置在基板上。 栅极氧化层设置在两个电荷俘获结构之间的衬底上。 栅极设置在栅极氧化物层和电荷捕获结构上，其中电荷捕获结构从栅极的两侧突出。 掺杂区域设置在栅极两侧的衬底中。

公开(公告)号：US20130009232A1

公开(公告)日：2013-01-10

申请号：US13177520

申请日：2011-07-06

Applicant: Chi-Cheng Huang ,  Ping-Chia Shih ,  Chih-Ming Wang ,  Chun-Sung Huang ,  Hsiang-Chen Lee ,  Chih-Hung Lin ,  Yau-Kae Sheu

Inventor： Chi-Cheng Huang ,  Ping-Chia Shih ,  Chih-Ming Wang ,  Chun-Sung Huang ,  Hsiang-Chen Lee ,  Chih-Hung Lin ,  Yau-Kae Sheu

IPC: H01L29/792 ,  H01L21/336

CPC classification number: H01L29/7923 ,  H01L29/66833

Abstract: A non-volatile memory cell includes a substrate, two charge trapping structures, a gate oxide layer, a gate and two doping regions. The charge trapping structures are disposed on the substrate separately. The gate oxide layer is disposed on the substrate between the two charge trapping structures. The gate is disposed on the gate oxide layer and the charge trapping structures, wherein the charge trapping structures protrude from two sides of the gate. The doping regions are disposed in the substrate at two sides of the gate.

Abstract translation: 非易失性存储单元包括衬底，两个电荷俘获结构，栅极氧化层，栅极和两个掺杂区域。 电荷捕获结构分别设置在基板上。 栅极氧化层设置在两个电荷俘获结构之间的衬底上。 栅极设置在栅极氧化物层和电荷捕获结构上，其中电荷捕获结构从栅极的两侧突出。 掺杂区域设置在栅极两侧的衬底中。

公开(公告)号：US20120216155A1

公开(公告)日：2012-08-23

申请号：US13033582

申请日：2011-02-23

Applicant: Ping-Chia Shih ,  Chun-Yao Wang ,  Chang-Yih Chen ,  Yau-Kae Sheu

Inventor： Ping-Chia Shih ,  Chun-Yao Wang ,  Chang-Yih Chen ,  Yau-Kae Sheu

IPC: G06F17/50

CPC classification number: G06F17/5081

Abstract: A method for checking mask design of an integrated circuit, wherein the integrated circuit includes a plurality of functional elements arranged at different positions, the method includes generating implant layer data of each functional element of the integrated circuit according to characteristics of each functional element; generating mask design data of the integrated circuit according to circuit design of the integrated circuit; generating a block diagram of the integrated circuit according to the mask design data; determining a corresponding position of the functional element in the block diagram according to the implant layer data; and comparing the implant layer data of the functional element with the mask design data at the corresponding position.

Abstract translation: 一种用于检查集成电路的掩模设计的方法，其中所述集成电路包括布置在不同位置的多个功能元件，所述方法包括根据每个功能元件的特性产生所述集成电路的每个功能元件的注入层数据; 根据集成电路的电路设计生成集成电路的掩模设计数据; 根据掩模设计数据生成集成电路的框图; 根据植入层数据确定框图中的功能元件的对应位置; 以及将所述功能元件的植入层数据与相应位置处的掩模设计数据进行比较。