公开(公告)号：US20220219970A1

公开(公告)日：2022-07-14

申请号：US17711067

申请日：2022-04-01

Applicant: XINTEC INC.

Inventor： Tsang-Yu LIU ,  Chaung-Lin LAI ,  Shu-Ming CHANG

IPC: B81B7/00 ,  B81C1/00

Abstract: A chip package includes a first die, a second die, a molding material, and a redistribution layer. The first die includes a first conductive pad. The second die is disposed on the first die and includes a second conductive pad. The molding material covers the first die and the second die. The molding material includes a top portion, a bottom portion, and an inclined portion adjoins the top portion and the bottom portion. The top portion is located on the second die, and the bottom portion is located on the first die. The redistribution layer is disposed along the top portion, the inclined portion, and the bottom portion. The redistribution layer is electrically connected to the first conductive pad and the second conductive pad.

公开(公告)号：US20230230933A1

公开(公告)日：2023-07-20

申请号：US18149029

申请日：2022-12-30

Applicant: XINTEC INC.

Inventor： Chia-Ming CHENG ,  Chaung-Lin LAI ,  Shu-Ming CHANG ,  Tsang-Yu LIU

IPC: H01L23/544 ,  H01L27/146

CPC classification number: H01L23/544 ,  H01L27/14618 ,  H01L27/14683 ,  H01L2223/54433

Abstract: A chip package includes a sensing element, a dam layer, and a light transmissive cover. A surface of the sensing element has a sensing area and a conductive pad. The conductive pad is adjacent to an edge of the surface of the sensing element. The dam layer is located on the surface of the sensing element and surrounds the sensing area. The dam layer has a main portion and plural mark portions. The mark portions are respectively located in plural corners of the main portion, located in a sidewall of the main portion, respectively located on plural corners of the sensing element, respectively located on plural inner edges of the main portion, or respectively located on plural outer edges of the main portion. The light transmissive cover is located on the dam layer.

公开(公告)号：US20230369371A1

公开(公告)日：2023-11-16

申请号：US17744664

申请日：2022-05-14

Applicant: XINTEC INC.

Inventor： Tsang-Yu LIU ,  Chaung-Lin LAI ,  Shu-Ming CHANG

IPC: H01L27/146 ,  H01L21/48

CPC classification number: H01L27/14634 ,  H01L21/481 ,  H01L21/4857 ,  H01L27/14627

Abstract: Chip packages and methods for forming the same are provided. The method includes providing a substrate having a chip region and a scribe-line region surrounding the chip region and forming a dielectric layer on an upper surface of the substrate. A dummy structure is formed in the dielectric layer over the scribe-line region of the substrate and extends along edges of the chip region. The dummy structure includes a first stack of dummy metal layers and a second stack of dummy metal layers arranged concentrically from the inside to the outside. The method also includes performing a sawing process on a portion of the dielectric layer that surrounds the dummy structure, so as to form a saw opening through the dielectric layer. At least the first stack of dummy metal layers remains in the dielectric layer after the sawing process is performed.

公开(公告)号：US20170256496A1

公开(公告)日：2017-09-07

申请号：US15440442

申请日：2017-02-23

Applicant: XINTEC INC.

Inventor： Chia-Sheng LIN ,  Chaung-Lin LAI ,  Kuei-Wei CHEN

IPC: H01L23/538 ,  H01L21/48 ,  H01L23/31 ,  H01L23/00

CPC classification number: H01L23/5389 ,  H01L21/4853 ,  H01L21/486 ,  H01L21/561 ,  H01L21/76898 ,  H01L23/3114 ,  H01L23/3171 ,  H01L23/5384 ,  H01L24/02 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L27/14618 ,  H01L27/14621 ,  H01L27/14627 ,  H01L27/14636 ,  H01L27/14683 ,  H01L2224/0231 ,  H01L2224/02331 ,  H01L2224/0235 ,  H01L2224/02372 ,  H01L2224/02377 ,  H01L2224/0239 ,  H01L2224/03462 ,  H01L2224/03464 ,  H01L2224/05008 ,  H01L2224/05111 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05169 ,  H01L2224/0529 ,  H01L2224/05548 ,  H01L2224/05569 ,  H01L2224/05582 ,  H01L2224/05611 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/05655 ,  H01L2224/05666 ,  H01L2224/05669 ,  H01L2224/11 ,  H01L2224/1132 ,  H01L2224/11462 ,  H01L2224/13211 ,  H01L2224/13216 ,  H01L2224/13244 ,  H01L2224/13247 ,  H01L2224/13255 ,  H01L2924/146 ,  H01L2924/19102 ,  H01L2924/301 ,  H01L2924/00014 ,  H01L2924/013 ,  H01L2924/06 ,  H01L2924/01074

Abstract: A chip package including a substrate is provided. A sensing region or device region of the substrate is electrically connected to a conducting pad. A first insulating layer is disposed on the substrate. A redistribution layer is disposed on the first insulating layer. A first portion and a second portion of the redistribution layer are electrically connected to the conducting pad. A second insulating layer conformally extends on the first insulating layer, and covers side surfaces of the first portion and the second portion. A protection layer is disposed on the second insulating layer. A portion of the second insulating layer is located between the protection layer and the first insulating layer. A method of forming the chip package is also provided.

公开(公告)号：US20170207182A1

公开(公告)日：2017-07-20

申请号：US15409289

申请日：2017-01-18

Applicant: XINTEC INC.

Inventor： Yen-Shih HO ,  Tsang-Yu LIU ,  Chia-Sheng LIN ,  Chaung-Lin LAI

IPC: H01L23/00 ,  H01L23/18 ,  H01L21/78 ,  H01L21/54 ,  H01L21/52 ,  H01L23/055 ,  H01L21/48

CPC classification number: H01L23/562 ,  H01L21/4817 ,  H01L21/52 ,  H01L21/54 ,  H01L21/76898 ,  H01L21/78 ,  H01L23/055 ,  H01L23/18 ,  H01L23/3114 ,  H01L23/522 ,  H01L24/16 ,  H01L25/065 ,  H01L27/14618 ,  H01L27/14687 ,  H01L2224/16237

Abstract: A chip package including a substrate is provided. The substrate has a first surface and a second surface opposite thereto. The substrate includes a sensing or device region which is adjacent to the first surface. A recess is in the substrate. The recess extends from the second surface towards the first surface, and vertically overlaps the sensing or device region. A redistribution layer is electrically connected to the sensing or device region, and extends from the second surface into the recess. A method of forming the chip package is also provided.

公开(公告)号：US20220285423A1

公开(公告)日：2022-09-08

申请号：US17683917

申请日：2022-03-01

Applicant: XINTEC INC.

Inventor： Tsang-Yu LIU ,  Shu-Ming CHANG ,  Chaung-Lin LAI

IPC: H01L27/146 ,  H01L23/544

Abstract: Chip packages and methods for forming the same are provided. The method includes providing a substrate having upper and lower surfaces, and having a chip region and a scribe-line region surrounding the chip region. The substrate has a dielectric layer on its upper surface. A masking layer is formed over the substrate to cover the dielectric layer. The masking layer has a first opening exposing the dielectric layer and extending in the extending direction of the scribe-line region to surround the chip region. An etching process is performed on the dielectric layer directly below the first opening, to form a second opening that is in the dielectric layer directly below the first opening. The masking layer is removed to expose the dielectric layer having the second opening. A dicing process is performed on the substrate through the second opening.

公开(公告)号：US20210032096A1

公开(公告)日：2021-02-04

申请号：US16941465

申请日：2020-07-28

Applicant: XINTEC INC.

Inventor： Tsang-Yu LIU ,  Chaung-Lin LAI ,  Shu-Ming CHANG

IPC: B81B7/00 ,  B81C1/00

Abstract: A chip package includes a first die, a second die, a molding material, and a redistribution layer. The first die includes a first conductive pad. The second die is disposed on the first die and includes a second conductive pad. The molding material covers the first die and the second die. The molding material includes a top portion, a bottom portion, and an inclined portion adjoins the top portion and the bottom portion. The top portion is located on the second die, and the bottom portion is located on the first die. The redistribution layer is disposed along the top portion, the inclined portion, and the bottom portion. The redistribution layer is electrically connected to the first conductive pad and the second conductive pad.

公开(公告)号：US20170098678A1

公开(公告)日：2017-04-06

申请号：US15280959

申请日：2016-09-29

Applicant: XINTEC INC.

Inventor： Chaung-Lin LAI ,  Wei-Ming CHIEN

IPC: H01L27/146

CPC classification number: H01L27/14636 ,  H01L27/14618 ,  H01L27/1462 ,  H01L27/14685 ,  H01L27/14687 ,  H01L2224/11

Abstract: This present invention provides a chip scale sensing chip package, comprising: a sensing chip with a first top surface and a first bottom surface opposite to each other, wherein the first top surface has a first insulating layer formed thereon, and the sensing chip comprises a sensing device adjacent to the first top surface and a plurality of conductive pads formed within the first insulating and adjacent to the sensing device, and a wiring layer formed on the first bottom surface to respectively connect to each of the conductive pads; and a dam formed on the first insulating layer adjacent to the sensing device.