公开(公告)号：US12028137B2

公开(公告)日：2024-07-02

申请号：US17890134

申请日：2022-08-17

Applicant: XILINX, INC.

Inventor： Ming Ruan

IPC: H04B7/06

CPC classification number: H04B7/0617 ,  H04B7/0626 ,  H04B7/0634

Abstract: Embodiments herein describe a radio unit (RU) of a radio access network (RAN), that extracts payload data and beamforming parameters from matrices received from a base station based on format parameters of the matrices and format parameters of channel state information resource signal resource elements (CSI-RS REs). The matrices include a payload matrix and first and second bit mask matrices. Locations of CSI-RS REs are determined based on the bit mask matrices. The payload matrix is separated into CSI-RS RE and non-CSI-RS RE payload matrices based on the locations of the CSI-RS REs. CSI-RS REs and the non-CSI-RS REs beamforming weight matrices are recovered from the bit mask matrices based on known features of the CSI-RS REs and the bit mask matrices. Digital downlink beamforming is performed based on the recovered payload matrices and beamforming weight matrices.

公开(公告)号：US09985654B1

公开(公告)日：2018-05-29

申请号：US15098709

申请日：2016-04-14

Applicant: Xilinx, Inc.

Inventor： Ming Ruan

IPC: H03M13/00 ,  H03M13/15

CPC classification number: H03M13/154 ,  H03M13/616

Abstract: An example method of erasure error correction in an IC includes receiving input data from a channel coupled to the IC, determining a bit pattern indicating survived blocks and erased blocks of a plurality of blocks in the input data and determining a number of integers, in a finite set of integers, greater than or less than an integer representing the bit pattern, the finite set of integers representing a finite set of possible values of the bit pattern based on an (m, k) erasure coding scheme. The method further includes generating an address for a memory, which stores a plurality of pre-computed decoding matrices based on the (m, k) erasure coding scheme, from the determined number of integers to obtain a pre-computed decoding matrix associated with the bit pattern. The method further includes recovering the erased blocks through matrix multiplication using the pre-computed decoding matrix and the survived blocks as parametric input.

公开(公告)号：US20230176819A1

公开(公告)日：2023-06-08

申请号：US17542016

申请日：2021-12-03

Applicant: Xilinx, Inc.

Inventor： Ming Ruan

IPC: G06F7/556 ,  G06F7/544 ,  G06F7/57

CPC classification number: G06F7/556 ,  G06F7/5443 ,  G06F7/57

Abstract: Circuits and methods for computing an order N polynomial include V decimation stages, each stage including respective multiply-and-accumulate circuitry. The multiply-and-accumulate circuitry in each stage k, in response to an input r-term and a plurality of input z-terms 0 through (Nk−1), generates output z-terms 0 through (Nk/2−1) and an output r-term as a square of the input r-term. Each output z-term i is a sum of input z-term (2i+1) of the input z-terms and a product of input z-term 2i and the input r-term. The multiply-and-accumulate circuitry in decimation stages k for k≤(V−1) provides the output r-term and one or more output z-terms from decimation stage k as the input r-term and one or more input z-terms to the respective multiply-and-accumulate circuitry of decimation stage k+1. A recursive stage inputs from decimation stage V, the output r-term as a recursive r-term and the output z-terms as a-terms, and generates a polynomial output value z by a recursive evaluation of the recursive r-term, the a-terms, and a modulus, p.

公开(公告)号：US20230142818A1

公开(公告)日：2023-05-11

申请号：US17523259

申请日：2021-11-10

Applicant: Xilinx, Inc.

Inventor： Ming Ruan

IPC: G06F7/544 ,  G06F7/523 ,  G06F7/50 ,  G06F7/72 ,  G06F5/01

CPC classification number: G06F7/5443 ,  G06F5/01 ,  G06F7/50 ,  G06F7/523 ,  G06F7/727

Abstract: Multiplication of integers over a finite field involves an array of arithmetic circuits configured to input a-limbs, d-limbs, and r-limbs. The array determines an intermediate term, Z, having z-limbs 0 through Kby determining respective sets of intermediate z-limbs 0 through K- 1 for r-limbs i for i = 0 to K - 1, and summing corresponding ones of the intermediate z-limbs of sets i through K - 1. The arithmetic circuits determine for r-limb 0, intermediate z-limbs 0 through K - 1 of set 0 as products of r-limb 0 and a-limbs 0 through K - 1, and for the remaining r-limbs determines intermediate z-limbs using different combinations of a-limbs, r-limbs, modulus, and d-limbs. A modulo circuit computes G as (most significant M bits of Z* m) + (least significant Q bits of Z, wherein M is a number of bits by which a number of bits of Z exceeds N, and Q is equal to M + ceil (log2 m), and increases G by m if bits Q through N - 1 of Z all having bit value one, and G ≥ 2Q - m. Circuitry assigns bits G bits 0 through Q-1 to Y bits 0 through Q- 1, and G bit Q to Y bit Q.

公开(公告)号：US11082067B1

公开(公告)日：2021-08-03

申请号：US16592381

申请日：2019-10-03

Applicant: XILINX, INC.

Inventor： Ming Ruan ,  Gordon I. Old ,  Richard L. Walke ,  Zahid Khan

IPC: H03M13/13 ,  G06F1/03 ,  G06F9/30 ,  H03M13/09

Abstract: Embodiments described herein provide a code generation mechanism (FIG. 3, 301) in a Polar encoder (FIG. 2, 204) to determine a bit type (FIG. 3, 312) corresponding to each coded bit in the Polar code before sending the data bits for encoding (FIG. 3, 303). For example, each bit in the Polar code is determined to have a bit type of a frozen bit, parity bit, an information bit, or a cyclic redundancy check (CRC) bit based at least on the respective reliability index of the bit from a pre-computed reliability index lookup table (FIG. 4A, 411). In this way, the bit type determination can be completed in one loop by iterating the list of entries in the pre-computed reliability index lookup table.

公开(公告)号：US10101969B1

公开(公告)日：2018-10-16

申请号：US15076345

申请日：2016-03-21

Applicant: Xilinx, Inc.

Inventor： Ming Ruan ,  Fengshou Guo

IPC: G06F7/72

Abstract: A system includes an integrated circuit configured to receive a multiplicand number, a multiplier number, and a modulus at one or more data inputs. The multiplicand number is partitioned into a plurality of multiplicand words. Each multiplicand word has a multiplicand word width. The multiplier number is partitioned into a plurality of multiplier words. Each multiplier word has a multiplier word width different from the multiplicand word width. A plurality of outer loop iterations of an outer loop is performed to iterate through the plurality of the multiplicand words. Each outer loop iteration of the outer loop includes a plurality of inner loop iterations of an inner loop performed to iterate through the plurality of the multiplier words. A Montgomery product of the multiplicand number and the multiplier number with respect to the modulus is determined.