公开(公告)号：US08271888B2

公开(公告)日：2012-09-18

申请号：US12358838

申请日：2009-01-23

申请人： William S. Carter ,  Guido D. Corona

发明人： William S. Carter ,  Guido D. Corona

IPC分类号： G06F3/048

CPC分类号： G06F3/011 ,  G06F3/016 ,  G06F3/04815 ,  G09B21/003 ,  G09B21/006

摘要： A method, a system, and a computer program product for providing a virtual probe, associated with an avatar, which enables blind or sightless navigation of an avatar through a virtual world. The system outputs tactile information and/or audible information that depict the presence of an object in the virtual world, in association with the avatar. When the virtual probe encounters an object in the virtual world the distance between the object and the avatar, a velocity of the object, and the dimensions of the object are determined. The tactile information, such as one or more vibrations, is output proportional to the distance between the object and the avatar and/or the dimension of the object. Audible information is also output in response to the detection of the object. Audible information, such as an audible voice, outputs one or more of the distance between the object and the avatar, the velocity of the object, and the dimensions of the object.

摘要翻译： 一种用于提供与化身相关联的虚拟探针的方法，系统和计算机程序产品，其能够通过虚拟世界盲人或无视地导航化身。 该系统输出与虚拟世界相关联的描绘虚拟世界中的对象的存在的触觉信息和/或听觉信息。 当虚拟探测器遇到虚拟世界中的对象时，确定对象和化身之间的距离，对象的速度和对象的尺寸。 诸如一个或多个振动的触觉信息与物体和化身之间的距离和/或物体的尺寸成比例地输出。 响应于对象的检测也输出声音信息。 诸如声音之类的声音信息输出物体和化身之间的距离，物体的速度和对象的尺寸中的一个或多个。

公开(公告)号：US08203561B2

公开(公告)日：2012-06-19

申请号：US12207588

申请日：2008-09-10

申请人： William S. Carter ,  Guido D. Corona

发明人： William S. Carter ,  Guido D. Corona

IPC分类号： G06T13/00 ,  G09G5/00

CPC分类号： A63F13/537 ,  A63F13/12 ,  A63F13/79 ,  A63F2300/5533 ,  G06T17/05 ,  G06T19/003

摘要： A computer implemented method, computer program product, and a data processing system determine an excursion corridor within a virtual environment. A time-stamped snapshot of a location of at least one avatar within the virtual universe is recorded. An avatar tracking data structure is then updated. The avatar tracking data structure provides a time-based history of avatar locations within the virtual universe. A weighted density map is generated. The weighted density map is then correlated with virtual object locations. Each virtual object location corresponds to a virtual object. Excursion corridors are identified. The excursion corridor identifies frequently taken routes between the virtual object locations. Waypoints are identified. Each waypoint corresponds to a virtual object. Each waypoint is an endpoint for one of the excursion corridors.

摘要翻译： 计算机实现的方法，计算机程序产品和数据处理系统确定虚拟环境内的偏移走廊。 记录虚拟宇宙中至少一个化身的位置的时间戳快照。 然后更新头像跟踪数据结构。 头像跟踪数据结构提供了虚拟世界中头像位置的基于时间的历史。 生成加权密度图。 然后将加权密度图与虚拟对象位置相关联。 每个虚拟对象位置对应于虚拟对象。 确定了游览走廊。 偏移走廊识别虚拟对象位置之间的经常拍摄的路线。 确定了航点。 每个航点对应一个虚拟对象。 每个航路点是其中一个偏移走廊的终点。

公开(公告)号：US20100060648A1

公开(公告)日：2010-03-11

申请号：US12207588

申请日：2008-09-10

申请人： William S. Carter ,  Guido D. Corona

发明人： William S. Carter ,  Guido D. Corona

IPC分类号： G06T15/70

CPC分类号： A63F13/537 ,  A63F13/12 ,  A63F13/79 ,  A63F2300/5533 ,  G06T17/05 ,  G06T19/003

摘要： A computer implemented method, computer program product, and a data processing system determine an excursion corridor within a virtual environment. A time-stamped snapshot of a location of at least one avatar within the virtual universe is recorded. An avatar tracking data structure is then updated. The avatar tracking data structure provides a time-based history of avatar locations within the virtual universe. A weighted density map is generated. The weighted density map is then correlated with virtual object locations. Each virtual object location corresponds to a virtual object. Excursion corridors are identified. The excursion corridor identifies frequently taken routes between the virtual object locations. Waypoints are identified. Each waypoint corresponds to a virtual object. Each waypoint is an endpoint for one of the excursion corridors.

摘要翻译： 计算机实现的方法，计算机程序产品和数据处理系统确定虚拟环境内的偏移走廊。 记录虚拟宇宙中至少一个化身的位置的时间戳快照。 然后更新头像跟踪数据结构。 头像跟踪数据结构提供了虚拟世界中头像位置的基于时间的历史。 生成加权密度图。 然后将加权密度图与虚拟对象位置相关联。 每个虚拟对象位置对应于虚拟对象。 确定了游览走廊。 偏移走廊识别虚拟对象位置之间的经常拍摄的路线。 确定了航点。 每个航点对应一个虚拟对象。 每个航路点是其中一个偏移走廊的终点。

公开(公告)号：US4706216A

公开(公告)日：1987-11-10

申请号：US706429

申请日：1985-02-27

申请人： William S. Carter

发明人： William S. Carter

IPC分类号： G11C19/28 ,  H03K3/037 ,  H03K5/1534 ,  H03K19/173 ,  G11C13/00

CPC分类号： G11C19/282 ,  H03K19/1733 ,  H03K19/1736 ,  H03K3/037 ,  H03K5/1534

摘要： A configurable logic circuit achieves versatility by including a configurable combinational logic element, a configurable storage circuit, and a configurable output select logic. The input signals to the configurable combinational logic element are input signals to the configurable logic circuit and feedback signals from the storage circuit. The storage circuit may be configured to operate as a D flip flop with or without set and reset inputs, an RS latch, a transparent latch with or without set and reset inputs, or as an edge detector. In conjunction with the combinational logic element, the storage circuit may also operate as a stage of a shift register or counter. The output select logic selects output signals from among the output signals of the combinational logic element and the storage circuit.

摘要翻译： 可配置逻辑电路通过包括可配置组合逻辑元件，可配置存储电路和可配置输出选择逻辑来实现多功能性。 到可配置组合逻辑元件的输入信号是到可配置逻辑电路的输入信号和来自存储电路的反馈信号。 存储电路可以被配置为作为D触发器操作，具有或不具有设置和复位输入，RS锁存器，具有或不具有置位和复位输入的透明锁存器，或作为边缘检测器。 结合组合逻辑元件，存储电路也可以作为移位寄存器或计数器的级进行操作。 输出选择逻辑从组合逻辑元件和存储电路的输出信号中选择输出信号。

公开(公告)号：US20130159848A1

公开(公告)日：2013-06-20

申请号：US13613547

申请日：2012-09-13

申请人： Christine A. Banke ,  William S. Carter ,  Pawan Khera ,  James R. Kraemer ,  Elizabeth V. Woodward

发明人： Christine A. Banke ,  William S. Carter ,  Pawan Khera ,  James R. Kraemer ,  Elizabeth V. Woodward

IPC分类号： G06F17/21 ,  G06F15/16

CPC分类号： G06F17/2735

摘要： A mechanism is provided for utilizing a dynamic personal dictionary in enhanced collaboration. A comparison is performed for each portion of entered text of the electronic communication with text identified in the dynamic personal dictionary. Responsive to a portion of the entered text matching an entry in the dynamic personal dictionary, the portion of the entered text is marked with an identifier, the identifier indicating that the portion of the entered text has an associated context definition. The electronic communication is then sent to a set of client devices with a set of marked text portions and associated identifiers.

公开(公告)号：US5267187A

公开(公告)日：1993-11-30

申请号：US944002

申请日：1992-09-11

申请人： Hung-Cheng Hsieh ,  William S. Carter ,  Charles S. Erickson ,  Edmond Y. Cheung

发明人： Hung-Cheng Hsieh ,  William S. Carter ,  Charles S. Erickson ,  Edmond Y. Cheung

IPC分类号： G06F7/50 ,  G06F7/57

CPC分类号： G06F7/57 ,  G06F7/503 ,  G06F7/5057 ,  G06F7/506

摘要： Programmable logic devices which include multiple blocks of combinatorial function generators and storage elements, and which are interconnected by a programmable interconnect structure are used, among other things for performing arithmetic functions which use logic for generating the carry function. When a large number of bits is to be processed, the carry function typically causes significant delay or requires significant additional components to achieve a result at high speed. The present invention provides dedicated hardware within the logic blocks for performing the carry function quickly and with a minimum number of components. The invention takes advantage of the fact that a carry signal to be added to two bits can be propagated to the next more significant bit when the two binary bits to be added are unequal, and that one of the bits can serve as the carry signal when the bits are equal.

摘要翻译： 使用包括组合函数发生器和存储元件的多个块并且通过可编程互连结构互连的可编程逻辑器件，用于执行使用用于产生进位功能的逻辑的算术功能。 当要处理大量的位时，进位功能通常会导致显着的延迟或需要大量附加组件以高速获得结果。 本发明提供逻辑块内的专用硬件，用于快速执行进位功能并具有最少数量的部件。 本发明利用以下事实：当要添加的两个二进制比特不相等时，要添加到两个比特的进位信号可以被传播到下一个更高有效比特，并且该比特中的一个可以用作进位信号，当 这些位是相等的。

公开(公告)号：US4855619A

公开(公告)日：1989-08-08

申请号：US121963

申请日：1987-11-17

申请人： Hung-Cheng Hsieh ,  William S. Carter

发明人： Hung-Cheng Hsieh ,  William S. Carter

IPC分类号： H03K19/003 ,  H03K19/0185 ,  H03K19/177

CPC分类号： H03K19/00361 ,  H03K19/018557 ,  H03K19/17712

摘要： A programmable interconnect for programmably connecting transmission lines which are part of a configurable logic array is combined with a buffer at locations within the logic array where a signal will travel from a low capacitance line to a higher capacitance line. Use of a buffer in this arrangement allows for programmable interconnects controlling the configuration of the logic array to be smaller; consuming less power and providing for faster rise and fall of an output signal even when propagating through a long series of programmable interconnects. Several arrangements for programmably controlling the interconnect are taught. Also taught is a means of achieving a very wide AND gate without the need for cascading smaller devices.

摘要翻译： 作为可配置逻辑阵列的一部分的可编程连接传输线的可编程互连与在逻辑阵列内的逻辑阵列中的缓冲器组合，其中信号将从低电容线行进到较高电容线。 在这种布置中使用缓冲器允许控制逻辑阵列的配置的可编程互连更小; 消耗较少的功率，并且即使在通过长串可编程互连传播时也能提供更快的输出信号上升和下降。 教导了可编程控制互连的几种布置。 还教导了实现非常宽的AND门的手段，而不需要级联较小的器件。

公开(公告)号：US07191342B1

公开(公告)日：2007-03-13

申请号：US10163152

申请日：2002-06-04

申请人： Bernard J. New ,  William S. Carter

发明人： Bernard J. New ,  William S. Carter

IPC分类号： H04L9/12 ,  G06F9/40 ,  G06F9/445 ,  G06F9/46

CPC分类号： G06F21/76 ,  H04L9/06 ,  H04L2209/12 ,  H04L2209/56

摘要： Described are methods and circuits that allow encrypted and unencrypted, or differently encrypted, configuration data to define the contents of the same physical memory frame or frames within a programmable logic device.

摘要翻译： 描述了允许加密和未加密或不同加密的配置数据来定义可编程逻辑设备内相同物理存储器帧或帧的内容的方法和电路。

公开(公告)号：US5295090A

公开(公告)日：1994-03-15

申请号：US66674

申请日：1993-05-24

申请人： Hung-Cheng Hsieh ,  William S. Carter ,  Charles S. Erickson ,  Edmond Y. Cheung

发明人： Hung-Cheng Hsieh ,  William S. Carter ,  Charles S. Erickson ,  Edmond Y. Cheung

IPC分类号： G06F7/50 ,  G06F7/506

CPC分类号： G06F7/506

摘要： Programmable logic devices which include multiple blocks of combinatorial function generators and storage elements, and which are interconnected by a programmable interconnect structure are used, among other things for performing arithmetic functions which use logic for generating the carry function. When a large number of bits is to be processed, the carry function typically causes significant delay or requires significant additional components to achieve a result at high speed. The present invention provides dedicated hardware within the logic blocks for performing the carry function quickly and with a minimum number of components. The invention takes advantage of the fact that a carry signal to be added to two bits can be propagated to the next more significant bit when the two binary bits to be added are unequal, and that one of the bits can serve as the carry signal when the bits are equal.

摘要翻译： 使用包括组合函数发生器和存储元件的多个块并且通过可编程互连结构互连的可编程逻辑器件，用于执行使用用于产生进位功能的逻辑的算术功能。 当要处理大量的位时，进位功能通常会导致显着的延迟或需要大量附加组件以高速获得结果。 本发明提供逻辑块内的专用硬件，用于快速执行进位功能并具有最少数量的部件。 本发明利用以下事实：当要添加的两个二进制比特不相等时，要添加到两个比特的进位信号可以被传播到下一个更高有效比特，并且该比特中的一个可以用作进位信号，当 这些位是相等的。

公开(公告)号：US4642487A

公开(公告)日：1987-02-10

申请号：US655007

申请日：1984-09-26

申请人： William S. Carter

发明人： William S. Carter

IPC分类号： H01L21/82 ,  H01L27/118 ,  H03K19/0175 ,  H03K19/173 ,  H03K19/177 ,  H03K19/20 ,  H03K17/693

CPC分类号： H03K19/17704

摘要： A special interconnect circuit which connects adjacent configurable logic elements (CLEs) in a configurable logic array (CLA) without using the general interconnect structure of the CLA. In one embodiment, an array of CLEs is arranged in rows and columns and a special vertical lead circuit is provided which connects an output lead of a given CLE in a given column to a selected input lead of the CLE above it and below in the same column. Special horizontal lead circuits are provided which connect a given output lead of a given CLE to a selected adjacent input lead of the CLE in the same row.

摘要翻译： 在可配置逻辑阵列（CLA）中连接相邻可配置逻辑元件（CLE）而不使用CLA的一般互连结构的特殊互连电路。 在一个实施例中，CLE阵列被布置成行和列，并且提供特殊的垂直引线电路，其将给定列中的给定CLE的输出引线连接到相同的CLE上方的CLE的选定输入引线 柱。 提供了特定的水平引线电路，其将给定CLE的给定输出引线连接到同一行中CLE的选定的相邻输入引线。