公开(公告)号：US20120104981A1

公开(公告)日：2012-05-03

申请号：US13046270

申请日：2011-03-11

申请人： Wei-Shuo Tseng ,  Chia-Pin Wei ,  Yu-Wei Lee

发明人： Wei-Shuo Tseng ,  Chia-Pin Wei ,  Yu-Wei Lee

IPC分类号： H02P27/00

CPC分类号： H02P6/001 ,  H02M3/158 ,  H02M3/33523 ,  H02M2001/007 ,  H02P6/34 ,  H02P2201/07

摘要： A driving device is electrically connected with an AC power and a brushless DC motor for a fan. The driving device includes a rectifier unit, a filter unit, a switch power conversion unit and a control unit. The rectifier unit receives the AC power and rectifies the AC power. The filter unit, electrically connected with the rectifier unit, filters the rectified AC power and generates a DC power. The switch power conversion unit, electrically connected with the filter unit and the brushless DC motor, receives the DC power and outputs a driving power to the brushless DC motor. The control unit is electrically connected with the switch power conversion unit and the brushless DC motor.

摘要翻译： 驱动装置与用于风扇的AC电力和无刷DC电动机电连接。 驱动装置包括整流单元，滤波单元，开关电源转换单元和控制单元。 整流单元接收交流电源并整流交流电源。 与整流单元电连接的滤波器单元对整流后的交流电进行滤波并产生直流电力。 与过滤器单元和无刷直流电动机电连接的开关电力转换单元接收直流电力并向无刷直流电动机输出驱动电力。 控制单元与开关电源转换单元和无刷直流电动机电连接。

公开(公告)号：US08558494B2

公开(公告)日：2013-10-15

申请号：US13046270

申请日：2011-03-11

申请人： Wei-Shuo Tseng ,  Chia-Pin Wei ,  Yu-Wei Lee

发明人： Wei-Shuo Tseng ,  Chia-Pin Wei ,  Yu-Wei Lee

IPC分类号： H02P27/00 ,  H02P6/00

CPC分类号： H02P6/001 ,  H02M3/158 ,  H02M3/33523 ,  H02M2001/007 ,  H02P6/34 ,  H02P2201/07

摘要： A driving device is electrically connected with an AC power and a brushless DC motor for a fan. The driving device includes a rectifier unit, a filter unit, a switch power conversion unit and a control unit. The rectifier unit receives the AC power and rectifies the AC power. The filter unit, electrically connected with the rectifier unit, filters the rectified AC power and generates a DC power. The switch power conversion unit, electrically connected with the filter unit and the brushless DC motor, receives the DC power and outputs a driving power to the brushless DC motor. The control unit is electrically connected with the switch power conversion unit and the brushless DC motor.

摘要翻译： 驱动装置与用于风扇的AC电力和无刷DC电动机电连接。 驱动装置包括整流单元，滤波单元，开关电源转换单元和控制单元。 整流单元接收交流电源并整流交流电源。 与整流单元电连接的滤波器单元对整流后的交流电进行滤波并产生直流电力。 与过滤器单元和无刷直流电动机电连接的开关电力转换单元接收直流电力并向无刷直流电动机输出驱动电力。 控制单元与开关电源转换单元和无刷直流电动机电连接。

公开(公告)号：US20050063240A1

公开(公告)日：2005-03-24

申请号：US10963573

申请日：2004-10-14

申请人： Yu-Wei Lee ,  Hsiao-Yang Hsu

发明人： Yu-Wei Lee ,  Hsiao-Yang Hsu

IPC分类号： G11C7/06 ,  G11C7/08 ,  G11C8/00

CPC分类号： G11C7/04 ,  G11C7/06

摘要： A control clocks generator and method thereof for a high speed sense amplifier generates control clocks by utilizing RC delay and gate delay, in combination with reference sensing delay induced from a reference sense amplifier, and thereby, is tracking well for the high speed sense amplifier with process, temperature and voltage variations.

公开(公告)号：US06947339B2

公开(公告)日：2005-09-20

申请号：US10963573

申请日：2004-10-14

申请人： Yu-Wei Lee ,  Hsiao-Yang Hsu

发明人： Yu-Wei Lee ,  Hsiao-Yang Hsu

IPC分类号： G11C7/06 ,  G11C7/08 ,  G11C7/00

CPC分类号： G11C7/04 ,  G11C7/06

摘要： A control clocks generator and method thereof for a high speed sense amplifier generates control clocks by utilizing RC delay and gate delay, in combination with reference sensing delay induced from a reference sense amplifier, and thereby, is tracking well for the high speed sense amplifier with process, temperature and voltage variations.

摘要翻译： 用于高速读出放大器的控制时钟发生器及其方法通过利用RC延迟和门延迟与从参考读出放大器引起的参考检测延迟相结合产生控制时钟，从而对于具有 过程，温度和电压变化。

公开(公告)号：US06867995B2

公开(公告)日：2005-03-15

申请号：US10457475

申请日：2003-06-10

申请人： Yu-Wei Lee ,  Sheau-Yung Shyu ,  Chih-Hung Wu

发明人： Yu-Wei Lee ,  Sheau-Yung Shyu ,  Chih-Hung Wu

IPC分类号： G11C17/12 ,  G11C17/00

CPC分类号： G11C17/12

摘要： A read only memory device includes multiple word lines, a first and second main bit line GL (n) and BL (n), sub-bit lines SB1 (n) to SB4 (n), selection switches MB1 (n) to MB4 (n), and memory cells M1 (n) to M4 (n). The memory cells M1 (n) to M4 (n) are electrically coupled to the sub-bit lines SB1 (n) to SB4 (n) and the sub-bit line SB1 (n+1), respectively. When the memory cell M3 (n) which is connected to SB3 (n) is read, the sub-bit lines SB1 (n) to SB3 (n) are connected to the corresponding main bit lines through the turned selection switches. At this time, the sub-bit lines SB1 (n) to SB3 (n) are not floating but are all at the same high voltage level. Therefore, the capacitance effect will not exist between them to change the voltage level of the sub-bit lines quickly.

摘要翻译： 只读存储器件包括多个字线，第一和第二主位线GL（n）和BL（n），子位线SB1（n）至SB4（n），选择开关MB1（n）至MB4（ n）和存储单元M1（n）〜M4（n）。 存储单元M1（n）至M4（n）分别电耦合到子位线SB1（n）至SB4（n）和子位线SB1（n + 1）。 当读取连接到SB3（n）的存储单元M3（n）时，子位线SB1（n）至SB3（n）通过转向选择开关连接到相应的主位线。 此时，子位线SB1（n）〜SB3（n）不浮动，但都处于相同的高电压电平。 因此，它们之间不会存在电容效应，以便快速改变子位线的电压电平。

公开(公告)号：US06839296B2

公开(公告)日：2005-01-04

申请号：US10458260

申请日：2003-06-11

申请人： Yu-Wei Lee ,  Hsiao-Yang Hsu

发明人： Yu-Wei Lee ,  Hsiao-Yang Hsu

IPC分类号： G11C7/06 ,  G11C7/08 ,  G11C7/00

CPC分类号： G11C7/04 ,  G11C7/06

摘要： A control clocks generator and method thereof for a high speed sense amplifier generates control clocks by utilizing RC delay and gate delay, in combination with reference sensing delay induced from a reference sense amplifier, and thereby, is tracking well for the high speed sense amplifier with process, temperature and voltage variations.

公开(公告)号：US06650148B1

公开(公告)日：2003-11-18

申请号：US10064373

申请日：2002-07-08

申请人： Yu-Wei Lee ,  Sheau-Yung Shyu

发明人： Yu-Wei Lee ,  Sheau-Yung Shyu

IPC分类号： G01R1900

CPC分类号： G11C7/065 ,  G11C2207/2281

摘要： A sense amplifier circuit for sensing data fed to its data input terminal and operating on the data according to a pre-charge signal, a latch signal and a sense amplifier enable signal. The sense amplifier circuit includes a pre-charge sense circuit that receives data from a data input terminal and outputs a first output value as well as a latching circuit that receives the first output value and outputs a second output value within a preset period. The pre-charge sense circuit further includes a first circuit and a second circuit. The first circuit is capable of pre-charging the data input terminal to a preset potential level. The second circuit produces a first output value according to the input data. In addition, the first circuit and the second circuit are connected in parallel between a voltage source and a data input terminal.

摘要翻译： 读出放大器电路，用于感测馈送到其数据输入端的数据，并根据预充电信号，锁存信号和读出放大器使能信号对数据进行操作。 读出放大器电路包括从数据输入端接收数据并输出第一输出值的预充电感测电路以及接收第一输出值并在预设时段内输出第二输出值的锁存电路。 预充电感测电路还包括第一电路和第二电路。 第一个电路能够将数据输入端子预充电到预设的电位电平。 第二电路根据输入数据产生第一输出值。 此外，第一电路和第二电路并联连接在电压源和数据输入端子之间。

公开(公告)号：US06421296B1

公开(公告)日：2002-07-16

申请号：US09849056

申请日：2001-05-04

申请人： Lai-Ching Lin ,  Yu-Wei Lee ,  Sheau-Yung Shyu

发明人： Lai-Ching Lin ,  Yu-Wei Lee ,  Sheau-Yung Shyu

IPC分类号： G11C300

CPC分类号： G11C16/0491 ,  G11C16/24 ,  G11C16/26

摘要： A double protection virtual ground memory circuit and column decoder. Through the introduction of a double protection circuit, leakage current from the virtual ground memory is reduced and power consumed by the memory circuit is lowered. Ultimately, sensing range of data within the memory by a sense amplifier is improved.

摘要翻译： 双重保护虚拟接地存储器电路和列解码器。 通过引入双重保护电路，来自虚拟接地存储器的泄漏电流降低，存储电路消耗的功率降低。 最终，由读出放大器感测存储器内的数据范围得到改善。

公开(公告)号：US06278649B1

公开(公告)日：2001-08-21

申请号：US09607730

申请日：2000-06-30

申请人： Yu-Wei Lee ,  Nien-Chao Yang

发明人： Yu-Wei Lee ,  Nien-Chao Yang

IPC分类号： G11C800

CPC分类号： G11C17/12 ,  G11C8/12

摘要： An integrated circuit memory comprises an array of non-volatile memory cells arranged in rows and columns, and including a plurality of banks. There are a plurality of word lines along the plurality of rows in the array, and a plurality of array bit lines arranged along the plurality of columns. The array bit lines extend across the array, and include sense lines and ground lines. A plurality of bank bit lines is arranged along the plurality of columns. The bank bit lines extend across corresponding banks in the plurality of banks and are coupled to memory cells in the corresponding banks. A plurality of connection terminals are coupled to the array bit lines. For each array bit line there is at least one connection terminal per bank in the plurality of banks for which the array bit line will be used. A plurality of bank select transistors is provided to act as bank select circuitry. The bank select transistors are operable to selectively connect respective bank bit lines to corresponding connection terminals for array bit lines. The bank select transistors are characterized by allowing independent connection of bank bit lines to sense lines of the plurality of array bit lines, while minimizing the number of transistors in the sensing path. In embodiments described, the bank select transistors allow independent connection of the bank bit lines to both sense lines and ground lines in the plurality of array bit lines.

摘要翻译： 集成电路存储器包括以行和列布置并且包括多个存储体的非易失性存储器单元阵列。 沿着阵列中的多个行存在多个字线，以及沿着多个列布置的多个阵列位线。 阵列位线延伸穿过阵列，并包括感测线和接地线。 沿着多个列布置多个行位线。 存储体位线在多个存储体中跨越相应的存储体并且耦合到相应存储体中的存储单元。 多个连接端子耦合到阵列位线。 对于每个阵列位线，在使用阵列位线的多个存储体中存在至少一个每个存储体的连接端子。 提供多个存储体选择晶体管用作存储体选择电路。 存储体选择晶体管可操作以选择性地将相应的存储体位线连接到阵列位线的对应连接端子。 存储体选择晶体管的特征在于允许独立连接组位线以感测多个阵列位线中的线，同时最小化感测路径中的晶体管的数量。 在所描述的实施例中，存储体选择晶体管允许组位线与多条阵列位线中的感测线和接地线的独立连接。