公开(公告)号：US06421296B1

公开(公告)日：2002-07-16

申请号：US09849056

申请日：2001-05-04

Applicant: Lai-Ching Lin ,  Yu-Wei Lee ,  Sheau-Yung Shyu

Inventor： Lai-Ching Lin ,  Yu-Wei Lee ,  Sheau-Yung Shyu

IPC: G11C300

CPC classification number: G11C16/0491 ,  G11C16/24 ,  G11C16/26

Abstract: A double protection virtual ground memory circuit and column decoder. Through the introduction of a double protection circuit, leakage current from the virtual ground memory is reduced and power consumed by the memory circuit is lowered. Ultimately, sensing range of data within the memory by a sense amplifier is improved.

Abstract translation: 双重保护虚拟接地存储器电路和列解码器。 通过引入双重保护电路，来自虚拟接地存储器的泄漏电流降低，存储电路消耗的功率降低。 最终，由读出放大器感测存储器内的数据范围得到改善。

公开(公告)号：US20090231176A1

公开(公告)日：2009-09-17

申请号：US12402501

申请日：2009-03-12

Applicant: Chih-Wei Chen ,  Lai-Ching Lin

Inventor： Chih-Wei Chen ,  Lai-Ching Lin

IPC: H03M1/66

CPC classification number: H03M1/0614 ,  H03M1/0682 ,  H03M1/667

Abstract: A switched capacitor digital-to-analog converter (SC-DAC) is provided. The SC-DAC of the present invention can eliminate an influence of a reference voltage source caused by a signal dependent loading at each clock cycle, so as to completely solve a harmonic distortion of an analog output signal converted by a conventional SC-DAC. In addition, when the SC-DAC of the present invention has a plurality of converting channels, since the reference voltage source is not influenced by the effect of signal dependent loading of any converting channel, so that each converting channel can be regarded to have a separate state, and thus the purpose of channel separation can be achieved.

Abstract translation: 提供开关电容数模转换器（SC-DAC）。 本发明的SC-DAC可以消除在每个时钟周期由信号相关负载引起的参考电压源的影响，以便完全解决由常规SC-DAC转换的模拟输出信号的谐波失真。 此外，当本发明的SC-DAC具有多个转换通道时，由于参考电压源不受任何转换通道的信号相关负载的影响的影响，使得每个转换通道可以被认为具有 分离状态，从而可以实现通道分离的目的。

公开(公告)号：US07830290B2

公开(公告)日：2010-11-09

申请号：US12402501

申请日：2009-03-12

Applicant: Chih-Wei Chen ,  Lai-Ching Lin

Inventor： Chih-Wei Chen ,  Lai-Ching Lin

IPC: H03M1/66

CPC classification number: H03M1/0614 ,  H03M1/0682 ,  H03M1/667

Abstract: A switched capacitor digital-to-analog converter (SC-DAC) is provided. The SC-DAC of the present invention can eliminate an influence of a reference voltage source caused by a signal dependent loading at each clock cycle, so as to completely solve a harmonic distortion of an analog output signal converted by a conventional SC-DAC. In addition, when the SC-DAC of the present invention has a plurality of converting channels, since the reference voltage source is not influenced by the effect of signal dependent loading of any converting channel, so that each converting channel can be regarded to have a separate state, and thus the purpose of channel separation can be achieved.

Abstract translation: 提供开关电容数模转换器（SC-DAC）。 本发明的SC-DAC可以消除在每个时钟周期由信号相关负载引起的参考电压源的影响，以便完全解决由常规SC-DAC转换的模拟输出信号的谐波失真。 此外，当本发明的SC-DAC具有多个转换通道时，由于参考电压源不受任何转换通道的信号相关负载的影响的影响，使得每个转换通道可以被认为具有 分离状态，从而可以实现通道分离的目的。

公开(公告)号：US06577536B1

公开(公告)日：2003-06-10

申请号：US10086379

申请日：2002-03-04

Applicant: Cheng-Lin Chung ,  Lai-Ching Lin ,  Nien-Chao Yang

Inventor： Cheng-Lin Chung ,  Lai-Ching Lin ,  Nien-Chao Yang

IPC: G11C1604

CPC classification number: G11C16/08 ,  G11C7/18 ,  G11C8/12

Abstract: A flat-cell nonvolatile semiconductor memory. The semiconductor memory includes a plurality of units. Each unit includes word lines, a main bit line, a ground line, sub-bit lines, memory cell columns, and bank-selecting switches. Word lines are disposed in parallel, and the main bit line and the ground line cross the word lines. Sub-bit lines are disposed substantially in parallel to the main bit lines. Each memory cell column includes a plurality of memory cells connected in parallel between respective adjacent two of the sub-bit lines. The bank-selecting switches are used to select one of the memory cell columns. The first one of the bank-selecting switches is disposed between the main bit line and the fourth sub-bit line. The second of the bank-selecting switches is disposed between the main bit line and the second sub-bit line. The third of the bank-selecting switches is disposed between the ground line and the fifth sub-bit line. The fourth of the bank-selecting switches is disposed between the ground line and the third sub-bit line. The fifth of the bank-selecting switch is disposed between the ground line and the third sub-bit line. The sixth bank-selecting switch is disposed between the ground line and the first sub-bit line. Wherein, the second, third, and fourth bank-selecting switches are controlled by a first selecting signal, and the first, fifth, and sixth bank-selecting switches are controlled by a second selecting signal.

Abstract translation: 一种扁平单元非易失性半导体存储器。 半导体存储器包括多个单元。 每个单元包括字线，主位线，地线，子位线，存储单元列和组选择开关。 字线平行设置，主位线和接地线与字线交叉。 子位线基本上平行于主位线布置。 每个存储单元列包括在相应的相邻两个子位线之间并联连接的多个存储单元。 银行选择开关用于选择一个存储单元列。 选择开关的第一个设置在主位线和第四子位线之间。 存储体选择开关中的第二个设置在主位线和第二子位线之间。 选择开关的三分之一设置在接地线和第五子位线之间。 选择开关的第四个设置在地线和第三子位线之间。 选择开关的第五个位于地线和第三子位线之间。 第六组选择开关设置在接地线和第一子位线之间。 其中，第二，第三和第四组选择开关由第一选择信号控制，第一，第五和第六组选择开关由第二选择信号控制。