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公开(公告)号：US20190139486A1
公开(公告)日：2019-05-09
申请号：US15312197
申请日：2016-09-18
Inventor： Yafeng LI
IPC: G09G3/3208 , G09G3/36
CPC classification number: G09G3/3208 , G09G3/36 , G09G3/3648 , G09G2310/0267 , G09G2310/08
Abstract: The present application discloses a scanning driving circuit and a flat display apparatus, the scanning driving circuit includes a plurality of cascaded scanning driving unit, each scanning driving unit including a forward and reverse scanning circuit for controlling the forward or reverse scanning; an input circuit to perform charging to the pull-up control signal point and the pull-down control signal point; an output circuit for generating a scanning driving signal with two-valued high electrical level and outputting to the current level scanning line to drive a pixel unit.
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2.发明申请公开(公告)号：US20180190201A1
公开(公告)日：2018-07-05
申请号：US15308557
申请日：2016-09-28
Inventor： Yafeng LI
IPC: G09G3/3266 , G09G3/36
CPC classification number: G09G3/3266 , G09G3/3674 , G09G3/3677 , G09G2310/0283 , G09G2310/0286 , G09G2320/0214
Abstract: The present application discloses a scanning driving circuit and a flat display apparatus, the scanning driving circuit includes a plurality of cascaded scanning driving unit, each scanning driving unit including a forward and reverse scanning circuit for controlling the forward or reverse scanning; an input circuit to perform charging to the pull-up control signal point and the pull-down control signal point; a leakage prevention circuit to preform a process to the leakage of the input circuit; an output circuit to generate a scanning driving signal and output to the level scanning line to drive a pixel unit.
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3.发明申请公开(公告)号：US20180136500A1
公开(公告)日：2018-05-17
申请号：US15126418
申请日：2016-06-30
Inventor： Yafeng LI
IPC: G02F1/1368 , G09G3/36
CPC classification number: G02F1/1368 , G09G3/36 , G09G3/3674
Abstract: The present disclosure proposes a GOA circuit based on LTPS TFTs. A ninth TFT is introduced to adjust the high and low voltage levels imposed on the second node P(n). The ninth TFT includes a gate and a source both electrically connected to the second node P(n) and a drain electrically connected to a second clock signal. Such designs make it possible that the level of the second node P(n) is pulled down according to a certain frequency when an output terminal G(n) keeps the low voltage level. So the second node P(n) does not need to keep the high voltage level all the time in the present invention. Also, the fourth and the seventh transistors T4 and T7 do not have the problem of a threshold voltage shift due to a long working time.
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公开(公告)号：US20250087180A1
公开(公告)日：2025-03-13
申请号：US18959687
申请日：2024-11-26
Inventor： Jian TAO , Shuai FENG , Yafeng LI , Zhong PENG , Jian HE
IPC: G09G3/36
Abstract: A multiplexed display panel includes sub-pixels, gate line, data lines, and a demultiplexer. The demultiplexer includes input channels each provided with switching transistors and fanout lines. Each fanout line is correspondingly connected to one data line by one switching transistor to provide one data signal to the one data line. The one switching transistor corresponding to each input channel is controlled by a same control signal. While each gate line scans one row of the sub-pixels, when a rising edge of the control signal reaches an amplitude, and at a moment when the one switching transistor is controlled by the control signal to be on, the demultiplexer is configured to make a difference between a potential reached by a rising edge of one fanout line correspondingly connected to the one data line and a potential of the one data line to be less than a preset threshold.
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公开(公告)号：US20190385552A1
公开(公告)日：2019-12-19
申请号：US15327303
申请日：2016-12-30
Inventor： Yafeng LI
IPC: G09G3/36
Abstract: Disclosed is a gate driving circuit and a display device, which belongs to the technical field of displaying, and resolves a technical problem that a signal transmitted between cascaded gate driving circuits is easily attenuated in the prior art. The gate driving circuit includes a precharging unit circuit, an output unit circuit, and a compensation charging unit circuit; the output unit circuit includes a first reference point and a first clock signal line; and the precharging unit circuit is configured to input a high level to the first reference point before an output period.
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Patent Agency Ranking
公开(公告)号：US20190096923A1
公开(公告)日：2019-03-28
申请号：US15744615
申请日：2017-12-21
Inventor： Yafeng LI , Jinfang WU
CPC classification number: H01L27/1244 , G06F3/0412 , H01L27/1248
Abstract: The present disclosure provides a display panel including a display area and a non-display area, a base substrate, a plurality of thin film transistors, a plurality of touch signal lines, a first test signal line area, an array substrate row driving circuit, a second test signal line area, a ground line area and an insulating layer. The thin film transistor includes a gate, a gate insulating layer, a source and a drain. The non-display area includes a first side and a second side; the array substrate row driving circuit respectively forms a first gap and a second gap with the first test signal line area and the second test signal line area, an orthographic projection of the ground line area on the base substrate is in the projection of the second test signal line area in the base substrate. The present disclosure also provides a display device.
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公开(公告)号：US20180217453A1
公开(公告)日：2018-08-02
申请号：US14897777
申请日：2015-11-05
Applicant: Shenzhen China Star Optoelectronics Technology Co. Ltd. , Wuhan China Star Optoelectronics Technology Co. Ltd.
Inventor： Yafeng LI , Jianhong LIN
IPC: G02F1/1343 , G02F1/1362 , G02F1/1368
CPC classification number: G02F1/134363 , G02F1/133514 , G02F1/13394 , G02F1/136209 , G02F1/136227 , G02F1/1368 , G02F2001/13396 , G02F2001/134318 , G02F2001/134345 , G02F2001/13685 , G02F2201/121 , G02F2201/122 , G02F2201/123 , G02F2202/104 , H01L27/12 , H01L27/124 , H01L27/1248 , H01L29/78633 , H01L29/78675
Abstract: Provided is an LTPS array substrate and a liquid crystal display panel, wherein the LTPS array substrate comprises: a first common electrode layer; a passivation layer, which is formed on the first common electrode layer, and has a first via hole formed therein; a pixel electrode layer, which is formed on the passivation layer; and a second common electrode layer, which is formed on the passivation layer, located between pixel electrodes corresponding to two adjacent sub-pixels in the pixel electrode layer, electrically isolated from the pixel electrode layer, and electrically connected to the first common electrode layer through the first via hole. The array substrate is capable of significantly enhancing the intensity of an electric field at an edge region of the adjacent sub-pixels, thereby increasing the transmittance at this region.
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公开(公告)号：US20240071331A1
公开(公告)日：2024-02-29
申请号：US17623328
申请日：2021-12-20
Inventor： Jian TAO , Shuai FENG , Yafeng LI , Zhong PENG , Jian HE
IPC: G09G3/36
CPC classification number: G09G3/3677 , G09G3/3688 , G09G2310/0297
Abstract: A multiplexed display panel and device and a driving method for the multiplexed display panel are provided. At the moment when a switching switch is turned on, a potential of a fanout line corresponding to a data line connected to sub-pixels, into which an data signal is input, is adjusted to the same level as a potential of the data line as much as possible, and a potential difference between each fanout line and the corresponding data line is relatively small at the moment when the switching switch is turned on, so that an instantaneous current at this moment is greatly reduced without causing relatively large jump of the potential of the data line, a common electrode and back-plated indium tin oxide (ITO) greatly fluctuate, and then the surface noise generated by the display panel is turned on is greatly reduced.
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公开(公告)号：US20180188581A1
公开(公告)日：2018-07-05
申请号：US15127389
申请日：2016-08-19
Inventor： Xiangyi PENG , Gui CHEN , Yafeng LI
IPC: G02F1/1333 , G02F1/1339 , G02F1/1343 , G02F1/1362 , G02F1/1368 , G06F3/041
CPC classification number: G02F1/13338 , G02F1/133345 , G02F1/13394 , G02F1/134363 , G02F1/13439 , G02F1/136209 , G02F1/136227 , G02F1/136286 , G02F1/1368 , G02F2001/13396 , G02F2001/134372 , G02F2001/13606 , G02F2001/136231 , G02F2001/136295 , G02F2001/13685 , G06F3/0412
Abstract: The present disclosure relates to an array substrate and the manufacturing method thereof, and a liquid crystal panel. The array substrate includes a transparent substrate; a gate line on the transparent substrate; a touch signal line on the same layer with the gate line, and the touch signal line is arranged on the transparent substrate; a dielectric layer covering the gate line and the touch signal line, and the dielectric layer is configured with at least one first through hole; and a touch electrode arranged on the dielectric layer, the touch electrode electrically connects to the touch signal line via the first through hole. In this way, the storage capacitance may be increased, and the pixels may be fully charged when the resolution rate is high. At the same time, the coupling capacitance between the touch electrode and the Rx signal line may be reduced.
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公开(公告)号：US20170236479A1
公开(公告)日：2017-08-17
申请号：US14906702
申请日：2015-12-20
Inventor： Yafeng LI
IPC: G09G3/36
CPC classification number: G09G3/3677 , G09G3/3648 , G09G3/3696 , G09G2230/00 , G09G2300/0408 , G09G2300/0809 , G09G2310/0286 , G11C19/28
Abstract: A GOA circuit includes GOA circuit units coupled in series. Each GOA circuit unit includes an input control module, an output control module, a pull-down module, and a pull-up holding module. The input control module includes a first transistor, a second transistor, a third transistor, and a fourth transistor. Each GOA circuit unit includes ten transistors. Because the GOA circuit unit proposed by the present invention comprises fewer transistors, it is good for being used in displays with a narrow bezel. In addition, the GOA circuit unit comprises an input control module comprising a second transistor and a third transistor controlled by a first gate turn-on signal. A first transistor and the second transistor are connected in series, and the third transistor and a fourth transistor are connected in series, which reduces leakage current. It provides a beneficiary effect that the stability of the GOA circuit unit is improved.
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