公开(公告)号：US20190081074A1

公开(公告)日：2019-03-14

申请号：US15577705

申请日：2017-09-06

Applicant: WUHAN CHINA STAR OPTOELECTRONICS TECHNOLOGY CO., LTD.

Inventor： Zhandong ZHANG

IPC: H01L27/12

Abstract: The present disclosure provides an array substrate and a method of manufacturing the same. The array substrate includes a substrate, a buffer layer, an active layer, a gate insulating layer with a second via hole, a gate, an interlayer insulating layer with a first via hole, a source electrode contacting the active layer through the first and second via holes, a planarization layer with a third via hole, a common electrode with a fourth via hole and a passivation layer sequentially disposed on the substrate, and a pixel electrode disposed on the passivation layer contacts the active layer through a fifth via hole passing through the fourth and third via holes, the interlayer insulating layer, and the gate insulating layer. According to present disclosure, static electricity generated in manufacturing is effectively prevented from being transferred to the active layer to cause Electro-Static discharge, which further improves the product quality.

公开(公告)号：US20190096927A1

公开(公告)日：2019-03-28

申请号：US15744174

申请日：2017-11-24

Applicant: WUHAN CHINA STAR OPTOELECTRONICS TECHNOLOGY CO., LTD

Inventor： Qi DING ,  Zhandong ZHANG ,  Li WANG

IPC: H01L27/12 ,  H01L21/027 ,  H01L21/266 ,  H01L29/66 ,  H01L29/786 ,  G03F1/32

Abstract: A manufacturing method of a thin film transistor is provided, which comprising the steps of: providing a substrate which includes a film layer; coating a photoresist material on the film layer to form a photoresist layer; executing an exposure process to the photoresist layer by using a mask, wherein the mask includes a central region and a boundary region surrounding the central region, a thickness of the central region is greater than that of the boundary region, and by having the thickness of the central region greater than that of the boundary region during the exposure process applied to the photoresist layer, loading effect happened during the development process is cancelled to uniformize a thickness of the film layer. A mask, a thin film transistor, and a display device are also provided in the present invention.

公开(公告)号：US20180097100A1

公开(公告)日：2018-04-05

申请号：US15109341

申请日：2016-05-04

Applicant: Wuhan China Star Optoelectronics Technology Co., Ltd.

Inventor： Zhandong ZHANG

IPC: H01L29/786 ,  H01L21/20 ,  H01L21/28 ,  G02F1/136 ,  H01L21/311

CPC classification number: H01L29/786 ,  G02F1/136 ,  G02F1/1368 ,  G02F2202/104 ,  H01L21/20 ,  H01L21/28 ,  H01L21/311 ,  H01L21/32155 ,  H01L27/127 ,  H01L27/1274

Abstract: The present invention provides a manufacture method of an array substrate, comprising steps of: depositing an active layer including amorphous silicon on a substrate; covering the active layer with a SiOx thin film; converting the amorphous silicon in the active layer into polysilicon; etching the active layer to form a pattern; implanting ion into the active layer; cleaning and removing the SiOx thin film. In the present invention, first, the SiOx thin film covers the active layer, and then processes of the conversion from amorphous silicon into polysilicon, etching the active layer and ion implantation are performed. After the ion is implanted into the active layer, the SiOx thin film is removed so that the active layer is always in the state covered by the thin film in the process to realize the technical result of reducing the pollution to the active layer.

公开(公告)号：US20180047757A1

公开(公告)日：2018-02-15

申请号：US14915225

申请日：2016-01-22

Applicant: Wuhan China Star Optoelectronics Technology Co., Ltd.

Inventor： Yu ZHAO ,  Zhandong ZHANG

IPC: H01L27/12 ,  G02F1/1368 ,  H01L29/786

CPC classification number: H01L27/1222 ,  G02F1/1368 ,  H01L27/127 ,  H01L29/78603 ,  H01L29/78696

Abstract: The present disclosure a semiconductor layer structure having an insulating substrate and a semiconductor layer formed on the insulating substrate. The semiconductor layer includes a source signal access terminal, a drain signal access terminal, a first semiconductor layer pattern and a second semiconductor layer pattern; the first semiconductor layer pattern and the second semiconductor layer pattern formed between the source signal access terminal and the drain signal access terminal in parallel. The present disclosure also provides a method for fabricating a semiconductor layer structure.