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公开(公告)号：US11101230B2
公开(公告)日：2021-08-24
申请号：US16308484
申请日：2018-09-27
Inventor： Chunpeng Guo , Yingchi Wang , Chunhung Huang
IPC: H01L23/00 , H01L27/12 , H01L25/18 , H01L25/00 , G02F1/1345 , H01L23/544
Abstract: The invention provides an array substrate and chip bonding method, the array substrate comprising: an active area, and a bonding area located around the active area, wherein the bonding area is provided with an input terminal group, a first output terminal group and a second output terminal a group; the first output terminal group is located at a side of the input terminal group away from the active area, and the second output terminal group is located between the first output terminal group and the input terminal group; when bonding chips, the first output terminal group or the second output terminal group is selected to cooperate with the input terminal group for chip bonding according to the chip type. By simultaneously providing the first and second output terminal groups, the bonding of the second type chip increases the distance between the chip and the edge of the array substrate.
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公开(公告)号：US20210091027A1
公开(公告)日：2021-03-25
申请号：US16308484
申请日：2018-09-27
Inventor： Chunpeng Guo , Yingchi Wang , Chunhung Huang
Abstract: The invention provides an array substrate and chip bonding method, the array substrate comprising: an active area, and a bonding area located around the active area, wherein the bonding area is provided with an input terminal group, a first output terminal group and a second output terminal a group; the first output terminal group is located at a side of the input terminal group away from the active area, and the second output terminal group is located between the first output terminal group and the input terminal group; when bonding chips, the first output terminal group or the second output terminal group is selected to cooperate with the input terminal group for chip bonding according to the chip type. By simultaneously providing the first and second output terminal groups, the bonding of the second type chip increases the distance between the chip and the edge of the array substrate.
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公开(公告)号：US10354567B2
公开(公告)日：2019-07-16
申请号：US15320764
申请日：2016-07-11
Inventor： Bin Xiong , Yingchi Wang , Chunhung Huang
IPC: G09G3/00 , H01L21/66 , G02F1/133 , G01R31/00 , G02F1/13 , G02F1/1333 , G06F3/041 , G09G3/36 , G09G3/3225
Abstract: A cell test method used for a fanout zone of a step location of a liquid crystal displays panel or an organic light emitting display panel, comprising the following steps: adding a cell test pad on an edge of a semi-finished flexible printed circuit board on glass (FOG) for the cell test method if length of the edge of the semi-finished FOG is greater than a critical value; placing alignment marks on the cell test pad; aligning the cell test pad by using the charge-coupled device; multiplexing process of some pins of the flexible printed circuit board to send signals for a cell test if the length of an edge of the semi-finished FOG is less than the critical value, controlling the signals to turn on by a metal oxide semiconductor.
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公开(公告)号：US09892671B2
公开(公告)日：2018-02-13
申请号：US14783728
申请日：2015-08-10
Inventor： Bin Xiong , Yingchi Wang , Gonghua Zou
CPC classification number: G09G3/2074 , G09G3/3607 , G09G3/3611 , G09G2320/0276 , G09G2320/0626 , G09G2320/0673 , G09G2360/145 , G09G2360/16
Abstract: A method of performing gamma correction for LCD panels includes: dividing the display area of a LCD panel to form n sub-areas of the display area; dividing all grey-scale images into n sets to form n sets of grey-scale images; displaying a first chosen grey-scale image of each set of grey-scale images on the corresponding sub-area of n sub-areas concurrently; detecting the brightness of the first chosen grey-scale image with a photosensor installed on the sub-area; examining if there is grey-scale image pending for detection in the set of grey scale images; extracting a gamma curve of the LCD panel; and correcting the gamma curve of the LCD panel.
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