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公开(公告)号:US12199108B2
公开(公告)日:2025-01-14
申请号:US17602793
申请日:2021-08-10
Inventor: Zuoyuan Xu , Ronglei Dai , Qiang Gong
IPC: H01L27/12
Abstract: The present disclosure discloses a display panel and a display device. The display panel comprises a driving chip and fan-out wires. Fan-out wires in a first fan-out wire group are electrically connected to corresponding output terminals through a second side of an adjacent driving chip; each of the fan-out wires in the first fan-out wire group comprises a first fan-out section and a second fan-out section that are connected and located on different layers. The present disclosure adopts a wire-changing jumper design to prevent signal disorder caused by inconsistent orders of the output terminals and the fan-out wires.
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公开(公告)号:US20240212577A1
公开(公告)日:2024-06-27
申请号:US17905253
申请日:2022-06-30
Inventor: Qiang Gong , Zuoyuan Xu , Ronglei Dai , Junhui Guo
IPC: G09G3/32
CPC classification number: G09G3/32 , G09G2300/0823 , G09G2310/0267 , G09G2310/0275 , G09G2330/022
Abstract: A display module, a driving method, and a display device are provided. The display module includes a display panel. The display panel includes a plurality of data lines, a plurality of scan lines, and a plurality of sub-pixels. The sub-pixels are respectively located in a plurality of sub-pixel areas defined by the scan lines and the data lines. The display panel further includes a neutralization circuit. The neutralization circuit includes at least one control terminal and at least two coupling terminals. The at least one control terminal is configured to control connection/disconnection between the at least two coupling terminals. The at least two coupling terminals are respectively electrically connected to at least two of the data lines.
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公开(公告)号:US10599242B2
公开(公告)日:2020-03-24
申请号:US15970589
申请日:2018-05-03
Inventor: Ronglei Dai
IPC: G06F3/041 , G09G3/36 , G02F1/1345
Abstract: The present application provides a single-type GOA circuit comprising a controllable signal setting unit for providing a controllable signal. The controllable signal is held at a potential of a constant low-level voltage source when the circuit is operated in normal status, and at a potential of a constant high-level voltage source when the circuit is in a transmission suspended period. The potential of the signals in the current leakage path in the transmission suspended period is changed in the application so that voltage controlling and leakage path eliminating could be achieved and stability of the circuit is increased.
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公开(公告)号:US11705043B2
公开(公告)日:2023-07-18
申请号:US16766832
申请日:2020-03-24
Inventor: Ronglei Dai , Zuoyuan Xu
IPC: G09G3/20
CPC classification number: G09G3/2003 , G09G2300/0408 , G09G2300/0443 , G09G2300/0452 , G09G2310/0297 , G09G2310/08 , G09G2340/0457
Abstract: A display panel includes an array substrate, a plurality of cascading GOA units, a plurality of DEMUX switching units, and a DEMUX control signal generating circuit. One DEMUX switching unit includes a scanning signal input port, at least two control signal input ports, and at least two scanning signal output ports. One GOA unit is connected to the scanning signal input port, the DEMUX control signal generating circuit is connected to the at least two control signal input ports, and the scanning signal output ports are connected to corresponding gate lines.
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公开(公告)号:US10796653B2
公开(公告)日:2020-10-06
申请号:US15748243
申请日:2017-11-27
Inventor: Ronglei Dai
IPC: G09G3/36
Abstract: A GOA circuit comprises m cascaded GOA units, wherein a GOA unit comprises forward-reverse scan control module, first gate signal output module and second gate signal output module. The forward-reverse scan control module controls the GOA circuit to perform forward scanning or reverse scanning. The first gate signal output module comprises seventh TFT, ninth TFT and sixteenth TFT; a second terminal of the sixteenth TFT receives a high potential signal, and a first and a third terminal of the sixteenth TFT are connected to the first and second terminals of the seventh TFT, respectively. The second gate signal output module comprises twelfth TFT, thirteenth TFT and fifteenth TFT; a second terminal of the fifteenth TFT receives the high potential signal, and a first and a third terminal of the fifteenth TFT are connected to the first and second terminals of the twelfth TFT, respectively.
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公开(公告)号:US09898984B2
公开(公告)日:2018-02-20
申请号:US14888426
申请日:2015-09-29
Applicant: Shenzhen China Star Optoelectronics Technology Co., Ltd. , Wuhan China Star Optoelectronics Technology Co., Ltd.
Inventor: Juncheng Xiao , Ronglei Dai , Yao Yan , Shangcao Cao
IPC: G09G3/36 , G02F1/1362
CPC classification number: G09G3/3674 , G02F1/1362 , G09G3/20 , G09G3/3648 , G09G2300/0408 , G09G2300/0434 , G09G2310/0202 , G09G2310/0218 , G09G2310/0267 , G09G2310/0286 , G11C19/287
Abstract: The invention discloses a GOA circuit, a display device and a drive method of a GOA circuit, the GOA circuit is set to be GOA units including a plurality of levels, a N leveled GOA unit is applied to charge a N leveled scanning line of a display region of the display device, the N leveled scanning line is connected to a first gate all on signal and a second gate all on signal, which can guarantee scanning lines corresponding to all the GOA units are being charged under control of the first gate all on signal and the second gate all on signal. The invention can carry out an all gate on function according to the method above.
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公开(公告)号:US09799293B2
公开(公告)日:2017-10-24
申请号:US14786071
申请日:2015-09-21
Applicant: Shenzhen China Star Optoelectronics Technology Co., Ltd. , Wuhan China Star Optoelectronics Technology Co., Ltd.
Inventor: Juncheng Xiao , Shangcao Cao , Yao Yan , Ronglei Dai
IPC: G09G3/36
CPC classification number: G09G3/3677 , G02F1/133 , G09G3/36 , G09G3/3696 , G09G2300/0408 , G09G2300/0871 , G09G2310/0202 , G09G2310/08
Abstract: A liquid crystal display device and a gate driving circuit are disclosed. The gate driving circuit includes multiple-stage gate driving units and a control chip. Each stage gate driving unit includes a first pulling control unit, a first pulling unit, a second pulling control unit, a second pulling unit, a first control unit, a second control unit and a third control unit. The control chip is used for pulling a first clock signal and a first voltage reference signal to a first voltage level. Accordingly, the scanning lines driven by the gate driving circuit are all turned on in order to stably realize an All-Gate-On function.
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公开(公告)号:US09607543B2
公开(公告)日:2017-03-28
申请号:US14779013
申请日:2015-08-07
Inventor: Sikun Hao , Xin Zhang , Ronglei Dai
IPC: G09G3/20 , G09G3/3266 , G09G3/36
CPC classification number: G09G3/2096 , G09G3/20 , G09G3/3266 , G09G3/3677 , G09G2300/0426 , G09G2300/0814 , G09G2310/0208 , G09G2310/0286 , G09G2310/0289 , G09G2310/0291
Abstract: A driving circuit is provided, a driving unit of the driving circuit includes: a control unit utilized to control an output of a stage transmission signal; a stage transmission signal latch unit utilized to receive the stage transmission signal for generating a latch signal; a first and second scanning signal generation units; a first inverted output unit utilized to invert the first scanning signal; a second inverted output unit utilized to invert the second scanning signal. A configuration of a GOA circuit can be simplified.
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公开(公告)号:US12205523B2
公开(公告)日:2025-01-21
申请号:US17905253
申请日:2022-06-30
Inventor: Qiang Gong , Zuoyuan Xu , Ronglei Dai , Junhui Guo
IPC: G09G3/32
Abstract: A display module, a driving method, and a display device are provided. The display module includes a display panel. The display panel includes a plurality of data lines, a plurality of scan lines, and a plurality of sub-pixels. The sub-pixels are respectively located in a plurality of sub-pixel areas defined by the scan lines and the data lines. The display panel further includes a neutralization circuit. The neutralization circuit includes at least one control terminal and at least two coupling terminals. The at least one control terminal is configured to control connection/disconnection between the at least two coupling terminals. The at least two coupling terminals are respectively electrically connected to at least two of the data lines.
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公开(公告)号:US09933889B2
公开(公告)日:2018-04-03
申请号:US15026595
申请日:2016-02-25
Inventor: Juncheng Xiao , Yao Yan , Shangcao Cao , Ronglei Dai
CPC classification number: G06F3/0416 , G06F3/0412 , G09G3/20 , G09G3/36 , G09G3/3659 , G09G3/3677 , G09G2300/0408 , G09G2300/0852 , G09G2300/0871 , G09G2310/021 , G09G2310/0245 , G09G2310/0281 , G09G2310/0283 , G09G2310/0286 , G09G2310/0289 , G09G2310/063 , G09G2310/08 , G09G2354/00 , G11C19/28
Abstract: Disclosed is a GOA driving circuit. In screen awakening stage, the first global control signal (Gas1) controls the twelfth thin film transistor (T12) to be activated for realizing the All Gate On function, and meanwhile controls the eleventh thin film transistor (T11) to be activated to pull down the voltage level of the second node (P(n)); in reset stage, the reset signal (Reset) controls the first thin film transistor (T1) to reset the voltage level of the second node (P(n)), and to set the duration of the single pulse of the reset signal (Reset) to be at least the sum of durations of initial pulses of the first, second clock signals; in touch scan stage, the second global control signal (Gas2) controls the thirteenth thin film transistor (T13) to be activated to make the output ends of the GOA units of the respective stages output composite signals (CS).
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