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公开(公告)号：US11056513B2
公开(公告)日：2021-07-06
申请号：US16162363
申请日：2018-10-16
Inventor： Xiaohui Nie , Jiawei Zhang
IPC: H01L27/12 , H01L27/02 , G02F1/1362
Abstract: The present disclosure discloses a thin film transistor array substrate, a display panel and a display device. The array substrate includes a substrate and an electrostatic discharge circuit layer, and the electrostatic discharge circuit layer is disposed in the non-display area at a side of the substrate and includes a conductive circuit disposed around the display area and electrostatic discharge devices electrically connected with the conductive circuit. The electrostatic discharge device includes a plurality of electrostatic discharge units disposed at intervals, one end of each of the electrostatic discharge units is connected with an edge of the substrate and the other end thereof is connected with the conductive circuit.
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公开(公告)号：US10901280B2
公开(公告)日：2021-01-26
申请号：US16252731
申请日：2019-01-21
Inventor： Pengfei Yu , Jiawei Zhang
IPC: H01L27/00 , G02F1/1362 , H01L27/12 , G02F1/1368 , H01L27/02
Abstract: An array substrate may include a display area and a non-display area surrounding the display area. The display area may include at least one antistatic wiring; and a plurality of scan lines. The at least one antistatic wiring may be configured to conduct static electricity, and the at least one antistatic wiring and the plurality of scan lines may be interlaced and insulated. The at least one antistatic wiring may include a first wiring portion and a second wiring portion adjacent to each other. The first wiring portion and the second wiring portion may be located in different layers.
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公开(公告)号：US10515984B1
公开(公告)日：2019-12-24
申请号：US15579250
申请日：2017-10-18
Inventor： Jiawei Zhang
IPC: H01L27/12 , H01L29/66 , H01L29/49 , H01L29/423 , H01L29/786
Abstract: A display panel, a display device and a method for preparing a low-temperature polysilicon thin film transistor are provided. The method includes: providing a base substrate; forming a semiconducting layer on the base substrate; forming a first insulating layer on the semiconducting layer; forming a first metal layer on the first insulating layer and pattering the first metal layer to obtain a first metal gate layer; forming a second insulating layer on the first metal layer; forming a second metal layer on the second insulating layer and patterning the second metal layer to obtain a second metal gate layer; forming a third insulating layer on the second metal layer; forming a third metal layer on the third insulating layer and patterning the third metal layer to form a source and a drain. The LTPS technology can be applied to the production of large-size panels by adopting the present disclosure.
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公开(公告)号：US11099440B2
公开(公告)日：2021-08-24
申请号：US16071525
申请日：2018-05-22
Inventor： Yuebai Han , Jiawei Zhang
IPC: G02F1/1362 , G02F1/1333 , G02F1/1368 , H01L27/12
Abstract: Provided are a display device and an array substrate thereof. The array substrate includes a plurality of pixel units arranged in an array, wherein each of the pixel units comprises a light shielding layer, a thin film transistor, a touch electrode, a scan line and a data line, and the scan line is disposed in a first direction, and the data line is disposed in a second direction, and the scan line crosses the data line, and the pixel unit further comprises a touch signal line, and the touch signal line is at a same layer as the scan line, and two adjacent touch signal lines in the first direction are connected with the light shielding layer, the touch signal line is connected to the light shielding layer through a first via hole, and the touch signal line is connected to the touch electrode through a second via hole.
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公开(公告)号：US10901282B2
公开(公告)日：2021-01-26
申请号：US16147880
申请日：2018-10-01
Inventor： Gaiping Lu , Jiawei Zhang , Wei Tang
IPC: G02F1/1368 , G02F1/1343 , H01L29/786 , G02F1/1362 , H01L27/12 , H01L21/768 , G02F1/1333 , H01L29/66 , G06F3/041
Abstract: The present disclosure provides a thin film transistor (TFT) substrate and a manufacturing method thereof. The TFT substrate include a TFT; a flat layer to cover the TFT; an opening hole defined in the flat layer and corresponding to a drain of the TFT; a bottom of the opening hole to retain a part of the flat layer for forming a flat layer sheet; a first metal layer formed on the flat layer; a first insulating layer formed on the first metal; a second metal formed on the first insulating layer and pass through the flat layer sheet for electrically connecting to the drain.
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Patent Agency Ranking
公开(公告)号：US10852606B2
公开(公告)日：2020-12-01
申请号：US16343782
申请日：2018-11-19
Inventor： Xiaohui Nie , Jiawei Zhang
IPC: G02F1/136 , G02F1/1362 , G02F1/1345 , G02F1/1368
Abstract: In an embodiment, a display panel circuit structure includes: a display area and an output bonding area located on a side of the display area. The output bonding area includes: a plurality of first bonding pads arranged in parallel at intervals, and a plurality of first connecting lines between corresponding first bonding pads of the first bonding pads. Each of the first bonding pads includes: a first bottom pad, a first middle pad, and a first top pad. The first bottom pad and the first connecting lines are all located at a first metal layer, the first middle pad is located at a second metal layer, the first top pad is located at a transparent, electrically conductive layer, the first metal layer, the second metal layer, and the transparent, electrically conductive layer are stacked in order.
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公开(公告)号：US20190235332A1
公开(公告)日：2019-08-01
申请号：US16147882
申请日：2018-10-01
Inventor： Pengfei Yu , Jiawei Zhang
IPC: G02F1/1362 , G09G3/36 , G02F1/1345 , G02F1/1335
Abstract: The present disclosure provides an array substrate, a display panel, and an electronic apparatus. The array substrate may include: multiple gate lines each extending along a first linear direction; and multiple data lines each extending along a second linear direction, wherein the multiple gate lines and the multiple data lines are interlaced with each other, the second linear direction is substantially perpendicular to the first linear direction; wherein a notch is defined on the upper edge. By the present disclosure, a wiring path of at least one of the gate lines or at least one of the data lines may avoid the notch. Therefore, a technical problem of uneven distribution of gate lines or data lines and abnormal display image due to the irregular shape of the display panel may be solved.
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公开(公告)号：US11092836B2
公开(公告)日：2021-08-17
申请号：US16068876
申请日：2018-04-24
Inventor： Pengfei Yu , Jiawei Zhang
IPC: G02F1/1333 , G06F3/041 , H01L27/12
Abstract: The present invention discloses an array substrate, including: a first metal layer, a second metal layer and a common electrode layer which are insulated from each other and sequentially formed on a base substrate; the first metal layer includes a gate line, the second metal layer includes a data line, and the common electrode layer includes a touch sensing electrode; the second metal layer includes a touch signal line, the touch signal line is electrically connected to the touch sensing electrode, and the touch signal line and the data line are intersected each other and are disconnected at an intersection location; and the first metal layer includes a bridging connection line, two ends of the bridging connection line are connected to the touch signal line such that the touch signal line disconnected at the intersection location are electrically connected. A manufacturing method and an in-cell touch panel are also disclosed.
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公开(公告)号：US20190294011A1
公开(公告)日：2019-09-26
申请号：US16252731
申请日：2019-01-21
Inventor： Pengfei Yu , Jiawei Zhang
IPC: G02F1/1362 , H01L27/12 , H01L27/02 , G02F1/1368
Abstract: An array substrate may include a display area and a non-display area surrounding the display area. The display area may include at least one antistatic wiring; and a plurality of scan lines. The at least one antistatic wiring may be configured to conduct static electricity, and the at least one antistatic wiring and the plurality of scan lines may be interlaced and insulated. The at least one antistatic wiring may include a first wiring portion and a second wiring portion adjacent to each other. The first wiring portion and the second wiring portion may be located in different layers.
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10.发明授权公开(公告)号：US10916641B2
公开(公告)日：2021-02-09
申请号：US16467046
申请日：2019-03-22
Inventor： Xiaohui Nie , Jiawei Zhang
IPC: H01L29/10 , H01L29/66 , H01L21/265 , H01L29/786
Abstract: The present application provides a thin film transistor, a method of manufacturing a thin film transistor, and a manufacturing system. The thin film transistor includes a substrate, a buffer layer, an active layer, and a gate insulating layer. A side area of the active layer is doped and modified, so that a surface of the side area is formed as a high resistance area, and then the gate insulating layer is formed by a chemical deposition process, thereby to avoid a weak channel current produced by unintentional electrically conduction of a boundary of the active layer due to a thinner thickness of the gate insulating layer when operating, thereby increasing electrical reliability of the thin film transistor.
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