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公开(公告)号：US10741111B2
公开(公告)日：2020-08-11
申请号：US15749422
申请日：2018-01-04
Inventor： Guanghui Hong
Abstract: A circuit and method for detecting pixel potential of a display panel and a display panel is provided. The circuit comprises a multiplexed output selector, at least one detection circuit and at least one signal amplifier. The detection circuit comprises a first TFT receiving a test signal and being connected to the multiplexed output selector. The multiplexed output selector is configured to selectively conduct the first data line, which is connected to a currently-detected sub-pixel unit, to the first TFT in accordance with a reverse clock signal to transmit a pixel potential signal of the currently-detected sub-pixel unit to the first TFT to control the first TFT to transmit the test signal to the signal amplifier. The signal amplifier is configured to receive and amplify the test signal to obtain and output a received signal. The present disclosure is able of measuring real pixel potential of the display panel.
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公开(公告)号：US10255864B2
公开(公告)日：2019-04-09
申请号：US15571011
申请日：2017-10-19
Inventor： Guanghui Hong
Abstract: The present application provides a demux control circuit. The demux control circuit includes a driving chip, a logic circuit, and a demux for providing two or three pulse signals to the logic circuit, the logic circuit including a plurality of NOR Gate and a plurality of buffers which can convert two pulse signals into three control signals or convert the three pulse signals into four control signals through the cooperation of the NOR gates and the buffers to achieve outputting a larger number of control signals by a smaller number of pins, thereby reducing the number of pins outputted from the driving chip and reduce production costs.
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公开(公告)号：US10741139B2
公开(公告)日：2020-08-11
申请号：US16069273
申请日：2018-02-22
Inventor： Guanghui Hong
IPC: G09G3/36
Abstract: A GOA circuit includes an output module in which a second TFT is arranged. The second TFT has a drain connected to a source of a first TFT, a gate receiving a first control signal, and a source receiving an Mth clock signal. The first control signal controls the second TFT to turn on and off. Alternatively, the drain of the second TFT is connected to the source of the first TFT, the gate receiving the Mth clock signal and the source connected to the first node to allow the second TFT to be conducted on only when the Mth clock signal is a high voltage and the first node is of a high voltage and is cut off at the remaining time. It is possible to prevent a voltage difference from being induced between the source and drain of the first TFT to reduce the electric current stress.
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公开(公告)号：US10446094B2
公开(公告)日：2019-10-15
申请号：US15319755
申请日：2016-08-19
Inventor： Guanghui Hong , Gui Chen , Qiang Gong
IPC: G09G3/36 , G02F1/133 , G02F1/1362 , G09G3/00
Abstract: The present disclosure provides a gate driver on array (GOA) circuit, where the GOA circuit includes a GOA driving chip, a GOA driving signal line, an array substrate test chip, a test signal line, and a GOA protecting circuit. The GOA driving chip is used to generate a scan driving signal. The GOA driving signal line is used to transmit the scan driving signal to a corresponding scan line. The array substrate test chip is used to generate an array substrate test signal. The test signal line is used to transmit the array substrate test signal to the corresponding scan line. The GOA protecting circuit is arranged between the GOA driving signal line and the test signal line.
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公开(公告)号：US10181301B2
公开(公告)日：2019-01-15
申请号：US15126409
申请日：2016-07-19
Inventor： Guanghui Hong , Qiang Gong
IPC: G09G3/36
Abstract: A liquid crystal display comprises a demultiplexer (Demux). The demultiplexer for the display comprises an integrated circuit unit and a logic unit electrically connected to the integrated circuit unit. The integrated circuit unit outputs three pulse signals including a first pulse signal, a second pulse signal, and a third pulse signal. The logic unit transforms the three pulse signals having different high and low voltage levels into at least four control signals.
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Patent Agency Ranking
公开(公告)号：US10833065B2
公开(公告)日：2020-11-10
申请号：US15740239
申请日：2017-10-21
Inventor： Guanghui Hong
IPC: H01L27/02 , G02F1/1362 , H01L27/12
Abstract: An array substrate and a display panel are disclosed. The array substrate includes: a GOA unit; a plurality of gate lines, electrically connected to the GOA unit; and a static-conducting device, electrically connected between the plurality of gate lines, in such a way that the plurality of gate lines are electrically connected to each other. In the array substrate, the static-conducting device is arranged between the plurality of gate lines, in such a way that the plurality of gate lines are electrically connected to each other to together resist the ESD. In this way, the anti-electrostatic discharge ability of the array substrate is improved, and the product quality is also improved.
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公开(公告)号：US10756120B2
公开(公告)日：2020-08-25
申请号：US15740985
申请日：2017-10-20
Inventor： Guanghui Hong
IPC: H01L27/12 , G02F1/133 , G02F1/1333 , G02F1/1343
Abstract: A thin film transistor array substrate and a display apparatus are disclosed. The thin film transistor array substrate includes a number of scan lines, data lines and pixel units. Each of the pixel units includes a thin film transistor and a pixel electrode. The thin film transistor includes a gate electrode, a source electrode and a drain electrode. The gate electrode is electrically connected to one of the scan lines, the source electrode is electrically connected to one of the data lines, and the drain electrode is electrically connected to the pixel electrode. The source electrode is arranged in a same layer as the data lines while the drain electrode and the source electrode are respectively arranged in different layers. Therefore, the implementation of the present disclosure may augment the PPI (Pixel units per Inch) of display apparatus without reducing its aperture ratio and product yield ratio.
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公开(公告)号：US10672356B2
公开(公告)日：2020-06-02
申请号：US15745109
申请日：2017-11-27
Inventor： Guanghui Hong
Abstract: The present application provides an NMOS type GOA circuit including: M cascaded GOA units, a Nth level GOA unit including: a forward reverse scan control circuit, a node signal control circuit, a node signal output circuit, a pull down circuit, and a output circuit; the forward reverse scan control circuit configured to perform a forward scan or a reverse scan according to a forward scan control signal or a reverse scan control signal; the output circuit including a first thin film transistor and a second thin film transistor, the node signal output circuit including a third thin film transistor, and the pull-down circuit including a fourth thin film transistor; wherein M≥N≥1, the high potential signal is a direct current signal, and the first and the drain terminal of the thin film transistor is one of a source and a drain, and the drain, the third terminal is a gate.
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公开(公告)号：US10381275B2
公开(公告)日：2019-08-13
申请号：US15749444
申请日：2018-01-02
Inventor： Guanghui Hong , Qiang Gong
IPC: H01L21/66 , H01L27/12 , H01L21/768 , H01L21/48 , G02F1/13
Abstract: The present invention provides an array substrate and an repairing method thereof, wherein the array substrate includes adjacent two level GOA unit circuits, wherein an output terminal of a Nth level GOA unit circuit is connected to a Nth level gate line, an output terminal of a N+1th level GOA unit circuit is connected to a N+1th level gate line; and a repairing structure disposed between the Nth level gate line and the N+1th level gate line, the repairing structure configured to turn on the Nth level gate line and the N+1th level gate line by melting when the Nth level GOA unit circuit or the N+1th level GOA unit circuit damaged. A repairing structure is added between two adjacent gate lines, when a certain GOA unit circuit is damaged, the repairing structure is melted by a laser to make the adjacent two gate lines communicate with each other.
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公开(公告)号：US10747076B2
公开(公告)日：2020-08-18
申请号：US15751945
申请日：2018-01-02
Inventor： Guanghui Hong , Qiang Gong
IPC: G09G3/36 , G02F1/1362
Abstract: The disclosure provides a display panel, a method for making the display panel, and a method for controlling the display panel. The display panel comprises: multiple gate lines and multiple data line crossing the multiple gate lines to form multiple pixel regions; multiple pixel electrodes in the multiple pixel regions; multiple first thin film transistors in the multiple pixel regions, the gates of the multiple first thin film transistors are connected to the gate lines, and the sources and the drains are connected to the data lines and the pixel electrodes respectively; and a second thin film transistor between and connecting two adjacent pixel electrodes, wherein the second thin film transistor is in a non-conducting state when the display panel is under normal operation, and the second thin film transistor is in a conducting state when the display panel is under a power failure condition.
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