公开(公告)号：US20230135072A1

公开(公告)日：2023-05-04

申请号：US18090510

申请日：2022-12-29

Applicant: United Microelectronics Corp.

Inventor： Hao Che Feng ,  Hung Jen Huang ,  Hsin Min Han ,  Shih-Wei Su ,  Ming Shu Chiu ,  Pi-Hung Chuang ,  Wei-Hao Huang ,  Shao-Wei Wang ,  Ping Wei Huang

IPC: H01L29/78 ,  H01L29/06 ,  H01L21/02 ,  H01L29/66 ,  H01L21/3105 ,  H01L21/311

Abstract: The invention provides a method for fabricating a fin structure for fin field effect transistor, including following steps. Providing a substrate, including a fin structure having a silicon fin and a single mask layer just on a top of the silicon fin, the single mask layer being as a top portion of the fin structure. Forming a stress buffer layer on the substrate and conformally covering over the fin structure. Performing a nitridation treatment on the stress buffer layer to have a nitride portion. Perform a flowable deposition process to form a flowable dielectric layer to cover over the fin structures. Annealing the flowable dielectric layer. Polishing the flowable dielectric layer, wherein the nitride portion of the stress buffer layer is used as a polishing stop.

公开(公告)号：US11862727B2

公开(公告)日：2024-01-02

申请号：US18090510

申请日：2022-12-29

Applicant: United Microelectronics Corp.

Inventor： Hao Che Feng ,  Hung Jen Huang ,  Hsin Min Han ,  Shih-Wei Su ,  Ming Shu Chiu ,  Pi-Hung Chuang ,  Wei-Hao Huang ,  Shao-Wei Wang ,  Ping Wei Huang

IPC: H01L29/78 ,  H01L29/06 ,  H01L21/02 ,  H01L29/66 ,  H01L21/3105 ,  H01L21/311

CPC classification number: H01L29/7854 ,  H01L21/0217 ,  H01L21/02247 ,  H01L21/31053 ,  H01L21/31111 ,  H01L21/31144 ,  H01L29/0649 ,  H01L29/66818

Abstract: The invention provides a method for fabricating a fin structure for fin field effect transistor, including following steps. Providing a substrate, including a fin structure having a silicon fin and a single mask layer just on a top of the silicon fin, the single mask layer being as a top portion of the fin structure. Forming a stress buffer layer on the substrate and conformally covering over the fin structure. Performing a nitridation treatment on the stress buffer layer to have a nitride portion. Perform a flowable deposition process to form a flowable dielectric layer to cover over the fin structures. Annealing the flowable dielectric layer. Polishing the flowable dielectric layer, wherein the nitride portion of the stress buffer layer is used as a polishing stop.

公开(公告)号：US10262869B2

公开(公告)日：2019-04-16

申请号：US15904405

申请日：2018-02-25

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Jen-Chieh Lin ,  Lee-Yuan Chen ,  Wen-Chin Lin ,  Chi-Lune Huang ,  Pi-Hung Chuang ,  Tai-Lin Chen ,  Sun-Hong Chen

IPC: H01L21/3105 ,  H01L21/308 ,  H01L21/768 ,  H01L21/321

Abstract: A planarization method includes providing a substrate having a semiconductor structure formed thereon. A dielectric layer is formed on the substrate, and a mask layer is formed on the dielectric layer. A first chemical mechanical polishing process is performed to remove a portion of the mask layer thereby forming an opening directly over the semiconductor structure and exposing the dielectric layer. A first etching process is performed to anisotropically remove a portion of the dielectric layer from the opening. The mask layer is then removed and a second chemical mechanical polishing process is then performed.

公开(公告)号：US11581438B2

公开(公告)日：2023-02-14

申请号：US16992061

申请日：2020-08-12

Applicant: United Microelectronics Corp.

Inventor： Hao Che Feng ,  Hung Jen Huang ,  Hsin Min Han ,  Shih-Wei Su ,  Ming Shu Chiu ,  Pi-Hung Chuang ,  Wei-Hao Huang ,  Shao-Wei Wang ,  Ping Wei Huang

IPC: H01L29/78 ,  H01L29/06 ,  H01L21/02 ,  H01L29/66 ,  H01L21/3105 ,  H01L21/311

Abstract: The invention provides a fin structure for a fin field effect transistor, including a substrate. The substrate includes a plurality of silicon fins, wherein a top of each one of the silicon fins is a round-like shape in a cross-section view. An isolation layer is disposed on the substrate between the silicon fins at a lower portion of the silicon fins while an upper portion of the silicon fins is exposed. A stress buffer layer is disposed on a sidewall of the silicon fins between the isolation layer and the lower portion of the silicon fins. The stress buffer layer includes a nitride portion.

公开(公告)号：US20180277382A1

公开(公告)日：2018-09-27

申请号：US15904405

申请日：2018-02-25

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Jen-Chieh Lin ,  Lee-Yuan Chen ,  Wen-Chin Lin ,  Chi-Lune Huang ,  Pi-Hung Chuang ,  Tai-Lin Chen ,  Sun-Hong Chen

IPC: H01L21/3105 ,  H01L21/321 ,  H01L21/768 ,  H01L21/308

CPC classification number: H01L21/31055 ,  H01L21/308 ,  H01L21/31053 ,  H01L21/31056 ,  H01L21/3212 ,  H01L21/76802

Abstract: A planarization method includes providing a substrate having a semiconductor structure formed thereon. A dielectric layer is formed on the substrate, and a mask layer is formed on the dielectric layer. A first chemical mechanical polishing process is performed to remove a portion of the mask layer thereby forming an opening directly over the semiconductor structure and exposing the dielectric layer. A first etching process is performed to anisotropically remove a portion of the dielectric layer from the opening. The mask layer is then removed and a second chemical mechanical polishing process is then performed.