公开(公告)号：US11101324B2

公开(公告)日：2021-08-24

申请号：US16513719

申请日：2019-07-17

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Da-Jun Lin ,  Bin-Siang Tsai ,  Ya-Jyuan Hung ,  Chin-Chia Yang ,  Ting-An Chien

IPC: H01L27/24 ,  H01L27/28 ,  H01L45/00 ,  H01L51/00 ,  H01L51/05 ,  H01L51/10

Abstract: A memory cell includes a first conductive line, a lower electrode, a carbon nano-tube (CNT) layer, a middle electrode, a resistive layer, a top electrode and a second conductive line. The first conductive line is disposed over a substrate. The lower electrode is disposed over the first conductive line. The carbon nano-tube (CNT) layer is disposed over the lower electrode. The middle electrode is disposed over the carbon nano-tube layer, thereby the lower electrode, the carbon nano-tube (CNT) layer and the middle electrode constituting a nanotube memory part. The resistive layer is disposed over the middle electrode. The top electrode is disposed over the resistive layer, thereby the middle electrode, the resistive layer and the top electrode constituting a resistive memory part. The second conductive line is disposed over the top electrode.

公开(公告)号：US20240290731A1

公开(公告)日：2024-08-29

申请号：US18660179

申请日：2024-05-09

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Da-Jun Lin ,  Chin-Chia Yang ,  Tai-Cheng Hou ,  Fu-Yu Tsai ,  Bin-Siang Tsai

IPC: H01L23/00 ,  H01L21/02 ,  H01L23/522 ,  H01L29/417

CPC classification number: H01L23/562 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02348 ,  H01L23/5226 ,  H01L29/41725

Abstract: A warpage-reducing semiconductor structure includes a wafer. The wafer includes a front side and a back side. Numerous semiconductor elements are disposed at the front side. A silicon oxide layer is disposed at the back side. A UV-transparent silicon nitride layer covers and contacts the silicon oxide layer. The refractive index of the UV-transparent silicon nitride layer is between 1.55 and 2.10.

公开(公告)号：US11632889B2

公开(公告)日：2023-04-18

申请号：US17375021

申请日：2021-07-14

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Da-Jun Lin ,  Bin-Siang Tsai ,  Ya-Jyuan Hung ,  Chin-Chia Yang ,  Ting-An Chien

IPC: H10B63/00 ,  H10K10/50 ,  H10K10/82 ,  H10K19/00 ,  H10K71/20 ,  H10K85/20 ,  H10N70/20 ,  H10N70/00

Abstract: A memory cell includes a first conductive line, a lower electrode, a carbon nano-tube (CNT) layer, a middle electrode, a resistive layer, a top electrode and a second conductive line. The first conductive line is disposed over a substrate. The lower electrode is disposed over the first conductive line. The carbon nano-tube (CNT) layer is disposed over the lower electrode. The middle electrode is disposed over the carbon nano-tube layer, thereby the lower electrode, the carbon nano-tube (CNT) layer and the middle electrode constituting a nanotube memory part. The resistive layer is disposed over the middle electrode. The top electrode is disposed over the resistive layer, thereby the middle electrode, the resistive layer and the top electrode constituting a resistive memory part. The second conductive line is disposed over the top electrode.

公开(公告)号：US20210343789A1

公开(公告)日：2021-11-04

申请号：US17375021

申请日：2021-07-14

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Da-Jun Lin ,  Bin-Siang Tsai ,  Ya-Jyuan Hung ,  Chin-Chia Yang ,  Ting-An Chien

IPC: H01L27/24 ,  H01L27/28 ,  H01L45/00 ,  H01L51/00 ,  H01L51/05 ,  H01L51/10

Abstract: A memory cell includes a first conductive line, a lower electrode, a carbon nano-tube (CNT) layer, a middle electrode, a resistive layer, a top electrode and a second conductive line. The first conductive line is disposed over a substrate. The lower electrode is disposed over the first conductive line. The carbon nano-tube (CNT) layer is disposed over the lower electrode. The middle electrode is disposed over the carbon nano-tube layer, thereby the lower electrode, the carbon nano-tube (CNT) layer and the middle electrode constituting a nanotube memory part. The resistive layer is disposed over the middle electrode. The top electrode is disposed over the resistive layer, thereby the middle electrode, the resistive layer and the top electrode constituting a resistive memory part. The second conductive line is disposed over the top electrode.

公开(公告)号：US20220392850A1

公开(公告)日：2022-12-08

申请号：US17369936

申请日：2021-07-07

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Da-Jun Lin ,  Chin-Chia Yang ,  Tai-Cheng Hou ,  Fu-Yu Tsai ,  Bin-Siang Tsai

IPC: H01L23/00 ,  H01L23/522 ,  H01L29/417 ,  H01L21/02

Abstract: A warpage-reducing semiconductor structure includes a wafer. The wafer includes a front side and a back side. Numerous semiconductor elements are disposed at the front side. A silicon oxide layer is disposed at the back side. A UV-transparent silicon nitride layer covers and contacts the silicon oxide layer. The refractive index of the UV-transparent silicon nitride layer is between 1.55 and 2.10.

公开(公告)号：US11094900B2

公开(公告)日：2021-08-17

申请号：US16241997

申请日：2019-01-08

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Da-Jun Lin ,  Bin-Siang Tsai ,  Chin-Chia Yang

IPC: H01L51/05 ,  H01L51/00 ,  H01L51/10

Abstract: A method for fabricating semiconductor device includes the steps of: forming a first metal interconnection in a first inter-metal dielectric (IMD) layer; performing a treatment process to rough a top surface of the first metal interconnection; and forming a carbon nanotube (CNT) junction on the first metal interconnection. Preferably, the treatment process further includes forming protrusions on the top surface of the first metal interconnection, in which the protrusions and the first metal interconnection comprise same material.

公开(公告)号：US20200185629A1

公开(公告)日：2020-06-11

申请号：US16241997

申请日：2019-01-08

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Da-Jun Lin ,  Bin-Siang Tsai ,  Chin-Chia Yang

IPC: H01L51/05 ,  H01L51/00 ,  H01L51/10

Abstract: A method for fabricating semiconductor device includes the steps of: forming a first metal interconnection in a first inter-metal dielectric (IMD) layer; performing a treatment process to rough a top surface of the first metal interconnection; and forming a carbon nanotube (CNT) junction on the first metal interconnection. Preferably, the treatment process further includes forming protrusions on the top surface of the first metal interconnection, in which the protrusions and the first metal interconnection comprise same material.

公开(公告)号：US12014995B2

公开(公告)日：2024-06-18

申请号：US17369936

申请日：2021-07-07

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Da-Jun Lin ,  Chin-Chia Yang ,  Tai-Cheng Hou ,  Fu-Yu Tsai ,  Bin-Siang Tsai

IPC: H01L23/00 ,  H01L21/02 ,  H01L23/522 ,  H01L29/417

CPC classification number: H01L23/562 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02348 ,  H01L23/5226 ,  H01L29/41725

Abstract: A warpage-reducing semiconductor structure includes a wafer. The wafer includes a front side and a back side. Numerous semiconductor elements are disposed at the front side. A silicon oxide layer is disposed at the back side. A UV-transparent silicon nitride layer covers and contacts the silicon oxide layer. The refractive index of the UV-transparent silicon nitride layer is between 1.55 and 2.10.

公开(公告)号：US20230361067A1

公开(公告)日：2023-11-09

申请号：US17735126

申请日：2022-05-03

Applicant: United Microelectronics Corp.

Inventor： Chin-Chia Yang ,  Da-Jun Lin ,  Fu-Yu Tsai ,  Bin-Siang Tsai

IPC: H01L23/00

CPC classification number: H01L24/08 ,  H01L24/80 ,  H01L2224/08145 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2924/05442 ,  H01L2924/05042 ,  H01L2924/059

Abstract: A semiconductor structure including a first substrate, a first dielectric layer, a first oxygen doped carbide (ODC) bonding layer, a second substrate, a second dielectric layer, and a second ODC bonding layer is provided. The first dielectric layer is located on the first substrate. The first ODC bonding layer is located on the first dielectric layer. The second dielectric layer is located on the second substrate. The second ODC bonding layer is located on the second dielectric layer. The first ODC bonding layer and the second ODC bonding layer are bonded to each other.

公开(公告)号：US11462513B2

公开(公告)日：2022-10-04

申请号：US17180909

申请日：2021-02-22

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chin-Chia Yang ,  Fu-Yu Tsai ,  Da-Jun Lin ,  Bin-Siang Tsai

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/544 ,  H01L21/768 ,  H01L25/00

Abstract: A chip bonding alignment structure includes a semiconductor chip, a metal layer, an etching stop layer, at least one metal bump, a dielectric barrier layer, a silicon oxide layer, and a silicon carbonitride layer. The metal layer is disposed on a bonding surface of the semiconductor chip and has a metal alignment pattern. The etching stop layer covers the bonding surface and the metal layer. The metal bump extends upward from the metal layer and penetrates through the etching stop layer. The dielectric barrier layer covers the etching stop layer and the metal bump. The silicon oxide layer covers the dielectric barrier layer. The silicon carbonitride layer covers the silicon oxide layer.