Invention Publication
- Patent Title: WARPAGE-REDUCING SEMICONDUCTOR STRUCTURE AND FABRICATING METHOD OF THE SAME
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Application No.: US18660179Application Date: 2024-05-09
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Publication No.: US20240290731A1Publication Date: 2024-08-29
- Inventor: Da-Jun Lin , Chin-Chia Yang , Tai-Cheng Hou , Fu-Yu Tsai , Bin-Siang Tsai
- Applicant: UNITED MICROELECTRONICS CORP.
- Applicant Address: TW Hsin-Chu City
- Assignee: UNITED MICROELECTRONICS CORP.
- Current Assignee: UNITED MICROELECTRONICS CORP.
- Current Assignee Address: TW Hsin-Chu City
- Priority: CN 2110630599.7 2021.06.07
- Main IPC: H01L23/00
- IPC: H01L23/00 ; H01L21/02 ; H01L23/522 ; H01L29/417

Abstract:
A warpage-reducing semiconductor structure includes a wafer. The wafer includes a front side and a back side. Numerous semiconductor elements are disposed at the front side. A silicon oxide layer is disposed at the back side. A UV-transparent silicon nitride layer covers and contacts the silicon oxide layer. The refractive index of the UV-transparent silicon nitride layer is between 1.55 and 2.10.
Information query
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